MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(2)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(3)
I(OHmax) = –2 mA(2)
I(OHmax) = –6 mA(3)
I(OLmax) = 1 mA(2)
I(OLmax) = 3 mA(3)
I(OLmax) = 2 mA(2)
I(OLmax) = 6 mA(3)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – Ports P1, P2, and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V
PMMCOREVx = 0
8
Port output frequency
(with load)
P3.4/TA2CLK/SMCLK/S27
fPx.y
MHz
20
CL = 20 pF, RL = 1 kΩ(1) or 3.2 kΩ(2)(3)
VCC = 3 V
PMMCOREVx = 3
VCC = 1.8 V
PMMCOREVx = 0
P1.0/TA0CLK/ACLK/S39
P3.4/TA2CLK/SMCLK/S27
P2.0/P2MAP0 (P2MAP0 = PM_MCLK )
CL = 20 pF(3)
8
fPort_CLK
Clock output frequency
MHz
20
VCC = 3 V
PMMCOREVx = 3
(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
(3) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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