MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 44. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h) (continued)
REGISTER DESCRIPTION
DMA Channel 4 source address high
REGISTER
DMA4SAH
OFFSET
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
DMA Channel 4 destination address low
DMA Channel 4 destination address high
DMA Channel 4 transfer size
DMA4DAL
DMA4DAH
DMA4SZ
DMA Channel 5 control
DMA5CTL
DMA5SAL
DMA5SAH
DMA5DAL
DMA5DAH
DMA5SZ
DMA Channel 5 source address low
DMA Channel 5 source address high
DMA Channel 5 destination address low
DMA Channel 5 destination address high
DMA Channel 5 transfer size
Table 45. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTL0
OFFSET
USCI control 0
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 1
UCA0CTL1
UCA0BR0
USCI baud rate 0
USCI baud rate 1
UCA0BR1
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA0IFG
UCA0IV
Table 46. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
UCB0CTL0
OFFSET
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB0CTL1
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
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