MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION
REGISTER
MAC32L
OFFSET
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control register 0
RES3
MPY32CTL0
Table 44. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION
DMA General Control: DMA module control 0
REGISTER
DMACTL0
OFFSET
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
DMA General Control: DMA module control 1
DMA General Control: DMA module control 2
DMA General Control: DMA module control 3
DMA General Control: DMA module control 4
DMA General Control: DMA interrupt vector
DMA Channel 0 control
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA0CTL
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA Channel 0 source address low
DMA Channel 0 source address high
DMA Channel 0 destination address low
DMA Channel 0 destination address high
DMA Channel 0 transfer size
DMA Channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA Channel 1 source address low
DMA Channel 1 source address high
DMA Channel 1 destination address low
DMA Channel 1 destination address high
DMA Channel 1 transfer size
DMA Channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA Channel 2 source address low
DMA Channel 2 source address high
DMA Channel 2 destination address low
DMA Channel 2 destination address high
DMA Channel 2 transfer size
DMA Channel 3 control
DMA3CTL
DMA3SAL
DMA3SAH
DMA3DAL
DMA3DAH
DMA3SZ
DMA Channel 3 source address low
DMA Channel 3 source address high
DMA Channel 3 destination address low
DMA Channel 3 destination address high
DMA Channel 3 transfer size
DMA Channel 4 control
DMA4CTL
DMA4SAL
DMA Channel 4 source address low
40
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