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MSP430F6630IPZR 参数 Datasheet PDF下载

MSP430F6630IPZR图片预览
型号: MSP430F6630IPZR
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号微控制器 [MIXED SIGNAL MICROCONTROLLER]
分类和应用: 微控制器
文件页数/大小: 116 页 / 1284 K
品牌: TI [ TEXAS INSTRUMENTS ]
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MSP430F663x  
www.ti.com  
SLAS566C JUNE 2010REVISED AUGUST 2012  
Peripheral File Map  
Table 20. Peripherals  
MODULE NAME  
BASE ADDRESS  
0100h  
0120h  
0140h  
0150h  
0158h  
015Ch  
0160h  
0180h  
01B0h  
01C0h  
01D0h  
0200h  
0220h  
0240h  
0260h  
0280h  
0320h  
0340h  
0380h  
03C0h  
0400h  
0480h  
04A0h  
04C0h  
0500h  
0510h  
0520h  
0530h  
0540h  
0550h  
0560h  
05C0h  
05E0h  
0600h  
0620h  
0700h  
0780h  
08C0h  
0900h  
0920h  
0A00h  
OFFSET ADDRESS RANGE(1)  
000h - 01Fh  
000h - 00Fh  
000h - 00Fh  
000h - 007h  
000h - 001h  
000h - 001h  
000h - 01Fh  
000h - 01Fh  
000h - 001h  
000h - 003h  
000h - 007h  
000h - 01Fh  
000h - 01Fh  
000h - 00Bh  
000h - 00Bh  
000h - 00Bh  
000h - 01Fh  
000h - 02Eh  
000h - 02Eh  
000h - 02Eh  
000h - 02Eh  
000h - 01Fh  
000h - 01Fh  
000h - 02Fh  
000h - 00Fh  
000h - 00Ah  
000h - 00Ah  
000h - 00Ah  
000h - 00Ah  
000h - 00Ah  
000h - 00Ah  
000h - 01Fh  
000h - 01Fh  
000h - 01Fh  
000h - 01Fh  
000h - 03Fh  
000h - 01Fh  
000h - 00Fh  
000h - 014h  
000h - 01Fh  
000h - 05Fh  
Special Functions (see Table 21)  
PMM (see Table 22)  
Flash Control (see Table 23)  
CRC16 (see Table 24)  
RAM Control (see Table 25)  
Watchdog (see Table 26)  
UCS (see Table 27)  
SYS (see Table 28)  
Shared Reference (see Table 29)  
Port Mapping Control (see Table 30)  
Port Mapping Port P2 (see Table 30)  
Port P1/P2 (see Table 31)  
Port P3/P4 (see Table 32)  
Port P5/P6 (see Table 33)  
Port P7/P8 (see Table 34)  
Port P9 (see Table 35)  
Port PJ (see Table 36)  
Timer TA0 (see Table 37)  
Timer TA1 (see Table 38)  
Timer TB0 (see Table 39)  
Timer TA2 (see Table 40)  
Battery Backup (see Table 41)  
RTC_B (see Table 42)  
32-bit Hardware Multiplier (see Table 43)  
DMA General Control (see Table 44)  
DMA Channel 0 (see Table 44)  
DMA Channel 1 (see Table 44)  
DMA Channel 2 (see Table 44)  
DMA Channel 3 (see Table 44)  
DMA Channel 4 (see Table 44)  
DMA Channel 5 (see Table 44)  
USCI_A0 (see Table 45)  
USCI_B0 (see Table 46)  
USCI_A1 (see Table 47)  
USCI_B1 (see Table 48)  
ADC12_A (see Table 49)  
DAC12_A (see Table 50)  
Comparator_B (see Table 51)  
USB configuration (see Table 52)  
USB control (see Table 53)  
LCD_B control (see Table 54)  
(1) For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide  
(SLAU208).  
Copyright © 2010–2012, Texas Instruments Incorporated  
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