MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Table 28. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Bootstrap loader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSRSTIV
Table 29. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
Table 30. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
REGISTER DESCRIPTION
REGISTER
PMAPPWD
Port mapping password register
Port mapping control register
Port P2.0 mapping register
Port P2.1 mapping register
Port P2.2 mapping register
Port P2.3 mapping register
Port P2.4 mapping register
Port P2.5 mapping register
Port P2.6 mapping register
Port P2.7 mapping register
00h
02h
00h
01h
02h
03h
04h
05h
06h
07h
PMAPCTL
P2MAP0
P2MAP1
P2MAP2
P2MAP3
P2MAP4
P2MAP5
P2MAP6
P2MAP7
Table 31. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
Port P1 direction
Port P1 pullup/pulldown enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
Port P2 direction
Port P2 pullup/pulldown enable
Port P2 drive strength
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