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DRV8860PW 参数 Datasheet PDF下载

DRV8860PW图片预览
型号: DRV8860PW
PDF下载: 下载PDF文件 查看货源
内容描述: 8通道串行接口低侧驱动器 [8 Channel Serial Interface Low-Side Driver]
分类和应用: 驱动器
文件页数/大小: 31 页 / 1394 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SLRS065A – SEPTEMBER 2013 – REVISED NOVEMBER 2013
PW (TSSOP) PACKAGE
(TOP VIEW)
VM
DIN
CLK
LATCH
GND
DOUT
nFAULT
ENABLE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
Pin Functions
NAME
GND
VM
PIN
5
1
I/O
(1)
DESCRIPTION
Device ground
Motor power supply
EXTERNAL COMPONENTS OR CONNECTIONS
All pins must be connected to ground
Connect to motor supply voltage. Bypass to GND with a 0.1μF ceramic capacitor
plus a 10μF electrolytic capacitor.
Logic high to enable outputs, logic low to disable outputs. Internal logic and
registers can be read and written to when ENABLE is logic low. Internal pulldown.
Refer to serial communication waveforms. Internal pulldown.
Rising edge clocks data into part for write operations. Falling edge clocks data out
of part for read operations. Internal pulldown.
Serial data input from controller. Internal pulldown.
Serial data output to controller. Open-drain output with internal pullup.
Logic low when in fault condition. Open-drain output requires external pullup.
Faults: OCP, OL, OTS, UVLO
NFET output driver. Connect external load between this pin and VM
NFET output driver. Connect external load between this pin and VM
NFET output driver. Connect external load between this pin and VM
NFET output driver. Connect external load between this pin and VM
NFET output driver. Connect external load between this pin and VM
NFET output driver. Connect external load between this pin and VM
NFET output driver. Connect external load between this pin and VM
NFET output driver. Connect external load between this pin and VM
POWER AND GROUND
CONTROL AND SERIAL INTERFACE
ENABLE
LATCH
CLK
DIN
DOUT
STATUS
nFAULT
OUTPUT
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
(1)
16
15
14
13
12
11
10
9
O
O
O
O
O
O
O
O
Low-side output 1
Low-side output 2
Low-side output 3
Low-side output 4
Low-side output 5
Low-side output 6
Low-side output 7
Low-side output 8
7
OD
Fault
8
4
3
2
6
I
I
I
I
O
Output stage enable
control input
Serial latch signal
Serial clock input
Serial data input
Serial data output
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
Critical Components
PIN
1
7
NAME
VM
nFAULT
COMPONENT
10µF electrolytic rated for VM voltage to GND,
0.1µF ceramic rated for VM voltage to GND
Requires external pullup to logic supply
Copyright © 2013, Texas Instruments Incorporated
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