SLRS065A – SEPTEMBER 2013 – REVISED NOVEMBER 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Functional Block Diagram
8 ~38 V
VM
10 µF
0.1µF
VM
4.5 V
Internal Reference
Regulators
UVLO
Gate Drive,
OCP,
OL
8 ~38 V
VM
OUT1
ENABLE
Gate Drive,
OCP,
OL
VM
OUT2
nFAULT
VM
Control Logic
and Registers
Gate Drive,
OCP,
OL
OUT3
VM
Gate Drive,
OCP,
OL
PWM
logic
OUT4
VM
Temperature
Sensor and
Thermal
Shutdown
Gate Drive,
OCP,
OL
OUT5
VM
LATCH
CLK
DIN
Gate Drive,
OCP,
OL
OUT6
VM
Serial
Interface
Gate Drive,
OCP,
OL
OUT7
DOUT
VM
Gate Drive,
OCP,
OL
OUT8
GND
2
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