DRV8860
SLRS065A –SEPTEMBER 2013–REVISED NOVEMBER 2013
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Output Energizing and PWM Control
The device output is defined by two stages: Energizing Phase and PWM Phase.
This special feature is designed to save energy and reduce heat for electromagnetic armature loads. It as well
can be used to adjust average output voltage for resistance load.
During the Energizing phase, the channel is turned on with 100% duty cycle for a duration set by Control register
bits C4:C1.
In PWM chopping phase, with the PWM Duty Cycle defined by Control register bits C7:C5.
The behavior of each bit in the Control Register is described in the table below:
CONTROL REGISTER SETTINGS
C8
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
C6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
C5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
C4
X
0
C3
X
0
C2
X
0
C1
X
0
Value
N/A
DESCRIPTION
Outputs always in Energizing mode
No Energizing, starts in PWM chopping
0 ms
0
0
0
1
3 ms
0
0
1
0
5 ms
0
0
1
1
10 ms
15 ms
20 ms
30 ms
50 ms
80 ms
110 ms
140 ms
170 ms
200 ms
230 ms
260 ms
300 ms
0%
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Sets the Energizing Time (100% duty cycle) before
switching to PWM Phase
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Output is off after Energizing Phase
0
0
1
12.50% 12.5 kHz
0
1
0
25.00%
37.50%
50.00%
62.50%
75.00%
87.50%
25 kHz
0
1
1
Sets PWM chopping duty cycle. DC is the
duty cycle that the low-side FET is on.
1
0
0
1
0
1
50 kHz
1
1
0
1
1
1
20
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