DRV8860
SLRS065A –SEPTEMBER 2013–REVISED NOVEMBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Functional Block Diagram
8 ~38 V
4.5 V
VM
8 ~38 V
Internal Reference
Regulators
UVLO
VM
VM
0.1µF
10 µF
Gate Drive,
OCP,
OL
OUT1
VM
ENABLE
nFAULT
Gate Drive,
OCP,
OL
OUT2
VM
Control Logic
and Registers
Gate Drive,
OCP,
OL
OUT3
OUT4
OUT5
OUT6
VM
Gate Drive,
OCP,
OL
PWM
logic
VM
Gate Drive,
OCP,
OL
Temperature
Sensor and
Thermal
Shutdown
VM
Gate Drive,
OCP,
OL
LATCH
CLK
VM
DIN
Gate Drive,
OCP,
OL
Serial
Interface
OUT7
DOUT
VM
Gate Drive,
OCP,
OL
OUT8
GND
2
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