SLES256 – MAY 2010
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illustrates cycle-by-cycle operation with high
side OC event and
shows cycle-by-cycle
operation with low side OC. Dashed lines are the
operation waveforms when no CBC event is triggered
and solide lines show the waveforms when CBC
event is triggered. In CBC current limiting mode,
when low side FET OC is detected, devcie will turn
off the affected low side FET and keep the high side
FET at the same half brdige off until next PWM cycle;
when high side FET OC is detected, devcie will turn
off the affected high side FET and turn on the low
side FET at the half brdige until next PWM cycle.
In OC latching shut down mode, the CBC current limit
and error recovery circuitries are disabled and an
overcurrent condition will cause the device to
shutdown immediately. After shutdown, RESET_A,
RESET_B, and / or RESET_C must be asserted to
restore normal operation after the overcurrent
condition is removed.
For added flexibility, the OC threshold is
programmable using a single external resistor
connected between the OC_ADJ pin and AGND pin.
See
for information on the correlation
between programming-resistor value and the OC
threshold.
Table 2. Programming-Resistor Values and OC
Threshold
OC-ADJUST RESISTOR
VALUES (kΩ)
19
(1)
It should be noted that a properly functioning
overcurrent detector assumes the presence of a
proper inductor or power ferrite bead at the
power-stage output. Short-circuit protection is not
guaranteed with direct short at the output pins of the
power stage.
Overtemperature Protection
The
DRV8312/32
have
a
two-level
temperature-protection system that asserts an
active-low warning signal (OTW) when the device
junction temperature exceeds 125°C (nominal) and, if
the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. OTSD is latched in this case and
RESET_A, RESET_B, and RESET_C must be
asserted low to clear the latch.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV8312/32 fully
protect the device in any power-up / down and
brownout situation. While powering up, the POR
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. The device automatically resumes
operation when all supply voltage on the bootstrap
capacitors have increased above the UVP threshold.
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
13.2
11.6
10.7
9.7
8.8
7.4
6.9
6.3
5.8
4.9
4.1
3.4
2.8
2.4
1.9
1.4
22
24
27
30
36
39
43
47
56
68
82
100
120
150
200
(1)
DEVICE RESET
Three reset pins are provided for independent control
of half-bridges A, B, and C. When RESET_X is
asserted low, two power-stage FETs in half-bridges X
are forced into a high-impedance (Hi-Z) state.
A rising-edge transition on reset input allows the
device to resume operation after a shut-down fault.
E.g., when half-bridge X has OC shutdown, a low to
high transition of RESET_X pin will clear the fault and
FAULT pin. When an OTSD occurs, all three
RESET_A, RESET_B, and RESET_C need to have a
low to high transition to clear the fault and reset
FAULT signal.
Recommended to use in OC Latching Mode Only
12
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