SLES256 – MAY 2010
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the DRV8312/32 need
only a 12-V supply in addition to H-Bridge power
supply (PVDD). An internal voltage regulator provides
suitable voltage levels for the digital and low-voltage
analog circuitry. Additionally, the high-side gate drive
requiring a floating voltage supply, which is
accommodated by built-in bootstrap circuitry requiring
external bootstrap capacitor.
To provide symmetrical electrical characteristics, the
PWM signal path, including gate drive and output
stage, is designed as identical, independent
half-bridges. For this reason, each half-bridge has a
separate gate drive supply (GVDD_X), a bootstrap
pin (BST_X), and a power-stage supply pin
(PVDD_X). Furthermore, an additional pin (VDD) is
provided as supply for all common circuits. Special
attention should be paid to place all decoupling
capacitors as close to their associated pins as
possible. In general, inductance between the power
supply pins and decoupling capacitors must be
avoided. Furthermore, decoupling capacitors need a
short ground path back to the device.
For a properly functioning bootstrap circuit, a small
ceramic capacitor (an X5R or better) must be
connected from each bootstrap pin (BST_X) to the
power-stage output pin (OUT_X). When the
power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected
between the gate-drive power-supply pin (GVDD_X)
and the bootstrap pin. When the power-stage output
is high, the bootstrap capacitor potential is shifted
above the output potential and thus provides a
suitable voltage supply for the high-side gate driver.
In an application with PWM switching frequencies in
the range from 10 kHz to 500 kHz, the use of 100-nF
ceramic capacitors (X5R or better), size 0603 or
0805, is recommended for the bootstrap supply.
These 100-nF capacitors ensure sufficient energy
storage, even during minimal PWM duty cycles, to
keep the high-side power stage FET fully turned on
during the remaining part of the PWM cycle. In an
application running at a switching frequency lower
than 10 kHz, the bootstrap capacitor might need to be
increased in value.
Special attention should be paid to the power-stage
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
half-bridge has independent power-stage supply pin
(PVDD_X). For optimal electrical performance, EMI
compliance, and system reliability, it is important that
each PVDD_X pin is decoupled with a ceramic
capacitor (X5R or better) placed as close as possible
to each supply pin. It is recommended to follow the
PCB layout of the DRV8312/32 EVM board.
The 12-V supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the
50-V power-stage supply is assumed to have low
output impedance and low noise. The power-supply
sequence is not critical as facilitated by the internal
power-on-reset circuit. Moreover, the DRV8312/32
are fully protected against erroneous power-stage
turn-on due to parasitic gate charging. Thus,
voltage-supply ramp rates (dv/dt) are non-critical
within the specified voltage range (see the
Recommended Operating Conditions
section of this
data sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The DRV8312/32 do not require a power-up
sequence. The outputs of the H-bridges remain in a
high impedance state until the gate-drive supply
voltage GVDD_X and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the
Electrical Characteristics
section of this data
sheet). Although not specifically required, holding
RESET_A, RESET_B, and RESET_C in a low state
while powering up the device is recommended. This
allows an internal circuit to charge the external
bootstrap capacitors by enabling a weak pulldown of
the half-bridge output.
Powering Down
The DRV8312/32 do not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the UVP voltage threshold
(see the
Electrical Characteristics
section of this data
sheet). Although not specifically required, it is a good
practice to hold RESET_A, RESET_B and RESET_C
low during power down to prevent any unknown state
during this transition.
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