Table 29. PHY Control Register (PHYCR), address 0x19 (Continued)
Bit
6
Bit Name
Default
0, RW
Description
LED_CNFG[1]
LED_CNFG[0]
LEDs Configuration
5
LED_CNFG[1]
LED_ CNFG[0]
Mode Description
Mode 1
Strap, RW
Don’t care
1
0
0
0
1
Mode 2
Mode 3
In Mode 1, LEDs are configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Activity, OFF for No Activity
In Mode 2, LEDs are configured as follows:
LED_LINK = ON for good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Collision, OFF for No Collision
Full Duplex, OFF for Half Duplex
In Mode 3, LEDs are configured as follows:
LED_LINK = ON for Good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Full Duplex, OFF for Half Duplex
PHY Address: PHY address for port.
4:0
PHYADDR[4:0]
Strap, RW
7.2.10 10Base-T Status/Control Register (10BTSCR)
Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A
Bit
Bit Name
Default
Description
10Base-T Serial Mode (SNI)
15
10BT_SERIAL
Strap, RW
1 = Enables 10Base-T Serial Mode
0 = Normal Operation
Places 10 Mb/s transmit and receive functions in Serial Network
Interface (SNI) Mode of operation. Has no effect on 100 Mb/s
operation.
14:12
11:9
RESERVED
SQUELCH
0, RW
RESERVED:
Must be zero.
100, RW
Squelch Configuration:
Used to set the Squelch ‘ON’ threshold for the receiver.
Default Squelch ON is 330mV peak.
8
LOOPBACK_10_D
IS
0, RW
In half-duplex mode, default 10BASE-T operation loops Transmit
data to the Receive data in addition to transmitting the data on the
physical medium. This is for consistency with earlier 10BASE2 and
10BASE5 implementations which used a shared medium. Setting
this bit disables the loopback function.
This bit does not affect loopback due to setting BMCR[14].
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TI [ TEXAS INSTRUMENTS ]
