capacitor values will vary with the crystal vendors; check
with the vendor for the recommended loads.
5.2 ESD Protection
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures
need be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo-
nents are less sensitive from ESD events.
The oscillator circuit is designed to drive a parallel reso-
nance AT cut crystal with a minimum drive level of 100µW
and a maximum of 500µW. If a crystal is specified for a
lower drive level, a current limiting resistor should be
placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, CL1 and CL2
should be set at 33 pF, and R1 should be set at 0Ω.
See Section 8.0 for ESD rating.
Specification for 25 MHz crystal are listed in Table 9.
5.3 Clock In (X1) Requirements
The DP83848I supports an external CMOS level oscillator
source or a crystal resonator device.
X2
X1
Oscillator
If an external clock source is used, X1 should be tied to the
clock source and X2 should be left floating.
R1
Specifications for CMOS oscillators: 25 MHz in MII Mode
and 50 MHz in RMII Mode are listed in Table 7 and Table 8.
CL1
CL2
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typi-
cal connection for a crystal resonator circuit. The load
Figure 12. Crystal Oscillator Circuit
Table 6.
Table 7. 25 MHz Oscillator Specification
Parameter
Frequency
Frequency
Tolerance
Frequency
Stability
Min
Typ
Max
+50
+50
Units
MHz
ppm
Condition
Operational Temperature
1 year aging
25
ppm
Rise / Fall Time
Jitter
6
nsec
psec
20% - 80%
Short term
8001
8001
Jitter
psec
Long term
Symmetry
40%
60%
Duty Cycle
1 This limit is provided as a guideline for component selection and to guaranteed by production testing.
Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.
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