4.2.7 Descrambler
4.2.10 100BASE-TX Link Integrity Monitor
A serial descrambler is used to de-scramble the received The 100 Base TX Link monitor ensures that a valid and sta-
NRZ data. The descrambler has to generate an identical ble link is established before enabling both the Transmit
data scrambling sequence (N) in order to recover the origi- and Receive PCS layer.
nal unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:
Signal detect must be valid for 395us to allow the link mon-
itor to enter the 'Link Up' state, and enable the transmit and
receive functions.
SD= (UD N)
UD= (SD N)
Synchronization of the descrambler to the original scram-
bling sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recog-
nized 12 consecutive IDLE code-groups, where an
unscrambled IDLE code-group in 5B NRZ is equal to five
consecutive ones (11111), it will synchronize to the receive
data stream and generate unscrambled data in the form of
unaligned 5B code-groups.
4.2.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83848I will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the
False Carrier Sense Counter register (FCSCR) will be
incremented by one.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data
that it generates. To ensure this, a line state monitor and a
hold timer are used to constantly monitor the synchroniza-
tion status. Upon synchronization of the descrambler the
hold timer starts a 722 µs countdown. Upon detection of
sufficient IDLE code-groups (58 bit times) within the 722 µs
period, the hold timer will reset and begin a new count-
down. This monitoring operation will continue indefinitely
given a properly operating network connection with good
signal integrity. If the line state monitor does not recognize
sufficient unscrambled IDLE code-groups within the 722 µs
period, the entire descrambler will be forced out of the cur-
rent state of synchronization and reset in order to re-
acquire synchronization.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
4.3 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compli-
ant. It includes the receiver, transmitter, collision, heart-
beat, loopback, jabber, and link integrity functions, as
defined in the standard. An external filter is not required on
the 10BASE-T interface since this is integrated inside the
DP83848I. This section focuses on the general 10BASE-T
system level operation.
4.2.8 Code-group Alignment
4.3.1 Operational Modes
The code-group alignment module operates on unaligned
5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and con-
verts it into 5B code-group data (5 bits). Code-group align-
ment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
The DP83848I has two basic 10BASE-T operational
modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83848I functions as a standard
IEEE 802.3 10BASE-T transceiver supporting the
CSMA/CD protocol.
4.2.9 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
Full Duplex Mode
In Full Duplex mode the DP83848I is capable of simulta-
5B code-groups are converted to the corresponding 4B neously transmitting and receiving without asserting the
nibbles for the duration of the entire packet. This conver- collision signal. The DP83848I's 10 Mb/s ENDEC is
sion ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.
designed to encode and decode simultaneously.
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