To tolerate potential frequency differences between the 50 The elasticity buffer will force Frame Check Sequence
MHz reference clock and the recovered receive clock, the errors for packets which overrun or underrun the FIFO.
receive RMII function includes a programmable elasticity Underrun and Overrun conditions can be reported in the
buffer. The elasticity buffer is programmable to minimize RMII and Bypass Register (RBR). The following table indi-
propagation delay based on expected packet size and cates how to program the elasticity buffer fifo (in 4-bit incre-
clock accuracy. This allows for supporting a range of ments) based on expected max packet size and clock
packet sizes including jumbo frames.
accuracy. It assumes both clocks (RMII Reference clock
and far-end Transmitter clock) have the same accuracy.
Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock
Start Threshold
RBR[1:0]
Latency Tolerance
Recommended Packet Size Recommended Packet Size
at +/- 50ppm
2400 bytes
7200 bytes
12000 bytes
16800 bytes
at +/- 100ppm
1200 bytes
3600 bytes
6000 bytes
8400 bytes
1 (4-bits)
2 (8-bits)
3 (12-bits)
0 (16-bits)
2 bits
6 bits
10 bits
14 bits
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83848I with a sequence that can be used to
establish synchronization. This preamble may be gener-
ated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resis-
tor to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition 32 MDC clock cycles
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.
3.3 10 Mb Serial Network Interface (SNI)
The DP83848I incorporates a 10 Mb Serial Network Inter-
face (SNI) which allows a simple serial data interface for 10
Mb only devices. This is also referred to as a 7-wire inter-
face. While there is no defined standard for this interface, it
is based on early 10 Mb physical layer devices. Data is
clocked serially at 10 MHz using separate transmit and
receive paths. The following pins are used in SNI mode:
— TX_CLK
— TX_EN
— TXD[0]
— RX_CLK
— RXD[0]
— CRS
The DP83848I waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83848I serial management port has been ini-
tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
— COL
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
3.4 802.3u MII Serial Management Interface
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid con-
tention during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround.
The addressed DP83848I drives the MDIO with a zero for
the second bit of turnaround and follows this with the
required data. Figure 4 shows the timing relationship
between MDC and the MDIO as driven/received by the Sta-
tion (STA) and the DP83848I (PHY) for a typical register
read access.
3.4.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces-
sible through the management interface pins MDC and
MDIO. The DP83848I implements all the required MII reg-
isters as well as several optional registers. These registers
are fully described in Section 7.0. A description of the serial
management access protocol follows.
For write transactions, the station management entity
writes data to the addressed DP83848I thus eliminating the
requirement for MDIO Turnaround. The Turnaround time is
filled by the management entity by inserting <10>. Figure 5
shows the timing relationship for a typical MII register write
access.
3.4.2 Serial Management Access Protocol
The serial control interface consists of two pins, Manage-
ment Data Clock (MDC) and Management Data Input/Out-
put (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for-
mat is shown below in Table 5.
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