Since the PHYAD[0] pin has weak internal pull-up resistor
and PHYAD[4:1] pins have weak internal pull-down resis-
tors, the default setting for the PHY address is 00001
(01h).
2.3 PHY Address
The 5 PHY address inputs pins are shared with the
RXD[3:0] pins and COL pin as shown below.
Refer to Figure 2 for an example of a PHYAD connection to
external components. In this example, the PHYAD strap-
ping results in address 00011 (03h).
Table 2. PHY Address Mapping
Pin #
42
PHYAD Function
PHYAD0
RXD Function
COL
43
PHYAD1
RXD_0
2.3.1 MII Isolate Mode
44
PHYAD2
RXD_1
The DP83848I can be put into MII Isolate mode by writing
to bit 10 of the BMCR register or by strapping in Physical
Address 0. It should be noted that selecting Physical
Address 0 via an MDIO write to PHYCR will not put the
device in the MII isolate mode.
45
PHYAD3
RXD_2
46
PHYAD4
RXD_3
The DP83848I can be set to respond to any of 32 possible
PHY addresses via strap pins. The information is latched
into the PHYCR register (address 19h, bits [4:0]) at device
power-up and hardware reset. The PHY Address pins are
shared with the RXD and COL pins. Each DP83848I or port
sharing an MDIO bus in a system must have a unique
physical address.
When in the MII isolate mode, the DP83848I does not
respond to packet data present at TXD[3:0], TX_EN inputs
and presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When
in Isolate mode, the DP83848I will continue to respond to
all management transactions.
While in Isolate mode, the PMD output pair will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
The DP83848I supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address
0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYCR
will not put the device in Isolate Mode. See Section 2.3.1for
more information.
The DP83848I can Auto-Negotiate or parallel detect to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the
receiver even when the DP83848I is in Isolate mode.
For further detail relating to the latch-in timing requirements
of the PHY Address pins, as well as the other hardware
configuration pins, refer to the Reset summary in
Section 6.0.
PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1
PHYAD4= 0
VCC
Figure 2. PHYAD Strapping Example
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