Table 5. Typical MDIO Frame Format
MII Management
Serial Protocol
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation
Write Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
MDC
Z
MDIO
(STA)
Z
Z
Z
MDIO
(PHY)
Z
Z
Z
0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
Opcode
(Read)
Register Address
(00h = BMCR)
PHY Address
Register Data
Idle
TA
Idle
Start
(PHYAD = 0Ch)
Figure 4. Typical MDC/MDIO Read Operation
MDC
Z
Z
MDIO
(STA)
Z
Z
0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PHY Address
Register Address
(00h = BMCR)
Opcode
(Write)
Register Data
Idle
Idle
Start
TA
(PHYAD = 0Ch)
Figure 5. Typical MDC/MDIO Write Operation
3.4.3 Serial Management Preamble Suppression
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Pre-
amble Suppression is supported.
The DP83848I supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Regis-
ter (BMSR, address 01h.) If the station management entity
(i.e. MAC or other management controller) determines that
all PHYs in the system support Preamble Suppression by
returning a one in this bit, then the station management
entity need not generate preamble for each management
transaction.
While the DP83848I requires an initial preamble sequence
of 32 bits for management initialization, it does not require
a full 32-bit sequence between each subsequent transac-
tion. A minimum of one idle bit between management
transactions is required as specified in the IEEE 802.3u
specification.
The DP83848I requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
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