DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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10 Mechanical
Table 10-1 shows the thermal resistance characteristics for the PBGA–AAR mechanical package.
The device package has been specially engineered with a new technology called Via Channel™, allowing
0.8 mm PCB design rules to be employed. This allows larger than normal PCB via and trace sizes and
reduced PCB signal layers to be used in a PCB design with this 0.5 mm pitch package, and will
substantially reduce PCB costs. It also allows PCB routing in only two signal layers (four layers total
deleted) due to the increased layer efficiency of the Via Channel™ BGA technology.
10.1 Thermal Data for the AAR
Table 10-1. Thermal Resistance Characteristics (PBGA Package) [AAR]
Air Flow (m/s)(1)
still air
ºC/W(2)
17.79
13.36
12.54
12.04
0.08
ΘJA/JMA
Junction-to-air/ Junction-to-moving air
Junction-to-package top
Junction-to-board
1.0 m/s
2.0 m/s
3.0 m/s
still air
PsiJT
1.0 m/s
2.0 m/s
3.0 m/s
still air
0.16
0.20
0.23
4.90
PsiJB
1.0 m/s
2.0 m/s
3.0 m/s
4.81
4.78
4.76
ΘJB
Junction-to-board
Junction-to-case
4.86
ΘJC (1SOP board)
3.84
(1) m/s = meters per second.
(2) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [ΘJC] measurement, which
was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information,
see these EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air).
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51-9, Test Boards for Area Array Surface Mount Packages.
10.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
276
Mechanical
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