8-BIT INTERFACE
The control logic of DAC811 permits interfacing to right-
justified data formats, as illustrated in Figure 9. When a
12-bit D/A converter is loaded from an 8-bit bus, two bytes
of data are required. Figures 10 and 11 show an addressing
scheme for right-justified and left-justified data respectively.
The base address is decoded from the high-order address
bits. A
0
and A
1
address the appropriate latches. Note that
adjacent addresses are used. For the right-justified case,
X10
16
loads the 8LSBs, and X01
16
loads the 4MSBs and
simultaneously transfers input latch data to the D/A latch.
Addresses X00
16
and X11
16
are not used.
Left-justified data is handled in a similar manner, shown in
Figure 11. The DAC811 still occupies two adjacent loca-
tions in the microcomputer's memory map.
16
DB0
10
17
DB1
9
18
DB2
8
19
DB3
7
Microcomputer
D0
D8
D1
D9
D2
D10
D3
D11
D4
D5
D6
D7
DAC811
DAC811
DB4
DB5
DB6
DB7
WR
14
13
12
11
2
A
15
16
DB0
14
10
17
DB1
13
9
18
DB2
12
8
19
DB3
11
7
WR
A
N
A
2
1
A
1
A
0
3
2
Base
Address
Decoder
7
6
5
4
2
D0
D4
D8
D1
D5
D9
D2
D6
D10
WR
A
2
A
1
Base
Address
Decoder
CS
3
4
LDAC
N
A
N
B
N
C
A
0
5
6
FIGURE 10. Right-Justified Data Bus Interface.
Microcomputer
DAC811
D3
D7
D11
WR
14
DB0
13
12
DB1
11
10
DB2
16
9
DB3
17
Microcomputer
D4
D5
D6
D7
D8
D0
D9
D1
D10
D2
D11
D3
CS
(Chip
Select)
Y
3
Y
2
Y
1
Y
0
3
4
5
6
LDAC
N
A
N
B
N
C
EN
A
1
A
0
1/2
74LS139
DB4
DB5
DB6
DB7
WR
8
18
7
19
FIGURE 8. Addressing and Control for 4-Bit Microcom-
puter Interface.
2
A
15
X
X
X
X
D11 D10
D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
WR
A
2
A
1
Base
Address
Decoder
CS
3
4
5
LDAC
N
A
N
B
N
C
a. Right-Justified
D11 D10
D9 D8 D7 D6 D5 D4
D3 D2 D1 D0
X
X
X
X
A
0
6
b. Left-Justified
FIGURE 9. 12-Bit Data Format for 8-Bit Systems.
FIGURE 11. Left-Justified Data Bus Interface.
®
DAC811
8
TI [ TEXAS INSTRUMENTS ]
