1
Percent of FSR per Percent of
Change of Power Supply Voltage
–V
CC
0.1
The D/A latch is controlled by LDAC and WR. LDAC and
WR are internally NORed so that the latches transmit data to
the D/A switches when both LDAC and WR are at logic 0.
When either LDAC or WR are at logic 1, the data is latched
in the D/A latch and held until LDAC and WR go to logic 0.
All latches are level-triggered. Data present when the con-
trol signals are logic 0 will enter the latch. When any one of
the control signals returns to logic 1, the data is latched.
Table II is a truth table for all latches.
WR
N
A
X
0
1
1
1
0
N
B
X
1
0
1
1
0
N
C
X
1
1
0
1
0
LDAC
X
1
1
1
0
0
OPERATION
No operation
Enables input latch 4MSBs
Enables input latch 4 middle bits
Enables input latch 4LSBs
Loads D/A latch from input latches
Makes all latches transparent
0.01
V
DD
0.001
+V
CC
0.0001
10
100
1k
10k
100k
1M
Frequency (Hz)
FIGURE 1. Power Supply Rejection vs Power Supply Ripple
Frequency.
1
0
0
0
0
0
“X” = Don’t care.
OPERATION
DAC811 is a complete single IC chip 12-bit D/A converter.
The chip contains a 12-bit D/A converter, voltage reference,
output amplifier, and microcomputer-compatible input logic
as shown in Figure 2.
INTERFACE LOGIC
Input latches A, B, and C hold data temporarily while a
complete 12-bit word is assembled before loading into the
D/A register. This double-buffered organization prevents the
generation of spurious analog output values. Each register is
independently addressable.
These input latches are controlled by N
A
, N
B
, N
C
, and WR.
N
A
, N
B
, and N
C
are internally NORed with WR so that the
input latches transmit data when both N
A
(or N
B
, N
C
) and
WR are at logic 0. When either N
A
, (N
B
, N
C
) or WR go to
logic 1, the input data is latched into the input registers and
held until both N
A
(or N
B
, N
C
) and WR go to logic 0.
TABLE II. DAC813 Interface Logic Truth Table.
GAIN AND OFFSET ADJUSTMENTS
Figures 3 and 4 illustrate the relationship of offset and gain
adjustments to unipolar and bipolar D/A converter output.
OFFSET ADJUSTMENT
For unipolar (USB) configurations, apply the digital input
code that should produce zero voltage output, and adjust the
offset potentiometer for zero output. For bipolar (BOB,
BTC) configurations, apply the digital input code that should
produce the maximum negative output voltage and adjust
the offset potentiometer for minus full scale voltage. Ex-
ample: If the full scale range is connected for 20V, the
maximum negative output voltage is –10V. See Table III for
corresponding codes.
MSB D11
7
WR
N
A
N
B
N
C
LDAC
2
8
9
D8
10
D7
11
12
13
D4
14
D3
19
18
17
D0
16
LSB
R
BPO
4-Bit Latch, A
4-Bit Latch, B
4-Bit Latch, C
27
BPO
SJ
10V
Range
4
5
R
F
6
3
12-Bit D/A Latch
R
F
12-Bit D/A Converter
24
Reference
V
OUT
25
26
Ref Out
28
23
ACOM
FIGURE 2. DAC811 Block Diagram.
®
5
DAC811
TI [ TEXAS INSTRUMENTS ]
