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SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009
DIGITAL INTERFACE
Timing
The serial interface is synchronous and controlled by the SCLK input. The DAC1220 latches incoming bits on the
falling edge of SCLK, and shifts outgoing bits on the rising edge of SCLK. An external interface should shift
outgoing bits on the rising edge of SCLK, and latch incoming bits on the falling edge of SCLK. The relevant
waveforms are illustrated in the timing diagrams (see
to
Timing numbers are given in
through
t
XIN
t
1
X
IN
t
2
Figure 7. X
IN
Clock Timing
Table 2. X
IN
Timing Characteristics
SYMBOL
f
XIN
t
XIN
t
1
t
2
X
IN
clock period
X
IN
clock high
X
IN
clock low
t
3
t
4
SCLK
t
6
SDIO
t
8
t
7
t
5
DESCRIPTION
X
IN
clock frequency
MIN
1
400
0.4 × t
XIN
0.4 × t
XIN
NOM
MAX
2.5
1000
UNITS
MHz
ns
ns
ns
Figure 8. Serial Input/Output Timing
Table 3. Serial I/O Timing Characteristics
SYMBOL
t
3
t
4
t
5
t
6
t
7
t
8
SCLK high
SCLK low
Data in valid to SCLK falling edge (setup)
SCLK falling edge to data in not valid (hold)
Data out valid to rising edge of SCLK (hold)
SCLK rising edge to new data out valid (delay)
DESCRIPTION
MIN
5 × t
XIN
5 × t
XIN
40
20
0
50
NOM
MAX
UNITS
ns
ns
ns
ns
ns
ns
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