SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009......................................................................................................................................
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THEORY OF OPERATION
The DAC1220 is a monolithic 20-bit delta-sigma (ΔΣ)
digital-to-analog converter (DAC) designed for
applications requiring extremely high precision. The
delta-sigma topology used in the DAC1220 ensures
20-bit monotonicity over the industrial temperature
range. The DAC1220 can also be operated in 16-bit
mode, which gives a faster settling time at the
expense of higher noise.
The core of the DAC1220 consists of an interpolation
filter and a second-order delta-sigma modulator. The
output of the modulator is passed to a first-order
switched-capacitor filter in series with a second-order
continuous-time filter, which generates the output
voltage.
To increase settling time, the DAC1220 can adjust its
filter cutoff frequency when it detects a voltage output
step of greater than approximately 40mV. This
behavior can be disabled.
An onboard self-calibration facility compensates for
internal offset and gain errors. Calibration values may
be stored and loaded externally if desired.
The DAC1220 can be put into a sleep mode, in which
power consumption is cut by about 1/6 to
approximately 0.45mW. In sleep mode, the output is
disconnected.
The DAC1220 is controlled using a synchronous
serial interface, using either two or three wires. The
interface may be operated bidirectionally or
unidirectionally; readback is optional.
+5V
4.7µF
Ceramic
Self-Calibration System
The self-calibration system of the DAC1220
measures the DAC output and calculates appropriate
gain and offset calibration constants. The output
changes during calibration, but can optionally be
disconnected during the procedure.
Offset calibration is performed by setting the DAC
output voltage to mid-scale and repeatedly comparing
the DAC output to the V
REF
voltage using an
auto-zeroed comparator, which is re-zeroed after
every comparison. The comparator results are
recorded and averaged, two’s complement adjusted,
and placed in the Offset Calibration Register.
Gain calibration is performed in a similar way, except
that
the
correction
is
done
against
an
internally-generated reference voltage, and the final
register value is calculated differently. The Full-Scale
Calibration Register result represents the gain code
and is not two’s complement adjusted. Changing the
Gain Register value can change the range of
voltages that are output for the same digital codes,
centered on V
REF
.
BASIC CONNECTIONS
A schematic showing basic connections to the
DAC1220 is given in
12pF
(1)
2.5MHz
12pF
(1)
+5V
DV
DD
X
OUT
X
IN
DGND
AV
DD
DNC
4.7µF
Ceramic
DNC
DNC
SCLK
SDIO
CS
AGND
V
REF
V
OUT
C
2
C
1
C
2(2)
SPI CLOCK
SPI DATA
From Chip Select or Ground
+2.5V from
Voltage Reference
V
OUT
C
1(2)
NOTES: (1) Depends on crystal and board layout. (2) See text for recommended values.
Figure 5. DAC1220 Schematic
6
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