CD74HC138-Q1
HIGH-SPEED CMOS LOGIC
3- TO 8-LINE INVERTING DECODER/DEMULTIPLEXER
SCLS580A − APRIL 2004 − REVISED APRIL 2008
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
E3
X
E2
X
X
H
L
E1
H
X
X
L
A2
A1
X
X
X
L
A0
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
X
X
L
X
X
X
L
L
X
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
L
L
H
H
H
H
L
L
H
H
NOTE: H = High voltage level, L = Low voltage level, X = Don’t care
logic diagram (positive logic)
15
Y0
1
2
3
A0
14
13
12
11
Y1
Y2
Y3
Y4
Select
Inputs
A1
Data
Outputs
A2
10
9
Y5
Y6
Y7
4
5
6
7
E1
E2
Enable
Inputs
E3
2
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