CC2510Fx / CC2511Fx
expansion is enabled by setting the
bit sample should be written to the
I2SCFG0.ULAWEbit to 1.
I2SDATH:I2SDATL
registers.
The
compression takes one clock cycle to perform,
and then the result can be read from the
I2SDATH register.
When the I2S interface is enabled, i.e. the
I2SCFG0.ENABbit is 1, and µ-Law expansion
is enabled, every byte of µ-Law compressed
data written to the I2SDATH register is
expanded to a 16-bit sample before being
transmitted. When the I2S interface is enabled
and µ-Law compression is enabled each
sample received is compressed to an 8-bit µ-
Law sample and put in the I2SDATHregister.
Only one of the flags I2SCFG0.ULAWC and
I2SCFG0.ULAWE should be set to 1 when the
I2SCFG0.ENABbit is 0.
12.15.13 I2S Registers
When the I2S interface is disabled, i.e. the
I2SCFG0.ENAB bit is 0, it can still be used to
perform µ-Law compression/expansion for
other resources in the system. To perform an
expansion, I2SCFG0.ULAWE must be 1 and
I2SCFG0.ULAWC must be 0 before writing a
byte of compressed data to the I2SDATH
register. The expansion takes one clock cycle
to perform, and then the result can be read
from the I2SDATH:I2SDATL registers.
This section describes all the registers used for
I2S control and status. The I2S registers reside
in XDATA memory space in the region 0xDF40
- 0xDF48. Table 33 on Page 49 gives an
overview of register addresses while the tables
in this section describe each register. Notice
that the reset values for the registers reflect a
configuration with 16-bit stereo samples and
44.1 kHz sample rate. The I2S is not enabled at
reset.
To perform a compression I2SCFG0.ULAWE
must be 0 and I2SCFG0.ULAWCmust be 1. To
start the compression, an un-compressed 16-
SWRS055F
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