CC2510Fx / CC2511Fx
followed by two positive edges on the 32 kHz
clock source. The code below shows how to
reset the Sleep Timer in combination with
updating EVENT0and/or entering PM{0 - 2}.
If EVENT0is changed to a value lower than the
current counter value, WORCTRL.WOR_RESET
has to be asserted first to reset the timer. The
assertion of WORCTRL.WOR_RESET must be
// Reset timer and enter PM{0 – 2}
WORCTRL |= 0x04;
// Reset Sleep Timer
// Wait until a positive 32 kHz edge
char temp = WORTIME0;
while(temp == WORTIME0);
temp = WORTIME0;
while(temp == WORTIME0);
PCON |= 0x01;
// Wait until a positive 32 kHz edge
// Enter PM{0 – 2}
// Reset timer and update EVENT0
WORCTRL |= 0x04;
// Reset Sleep Timer
char temp = WORTIME0;
while(temp == WORTIME0);
// Wait until a positive 32 kHz edge
temp = WORTIME0;
while(temp == WORTIME0);
WOREVT1 = desired event0 >> 8;
WOREVT0 = desired event0;
// Wait until a positive 32 kHz edge
// Set EVENT0, high byte
// Set EVENT0, low byte
// Reset timer, update EVENT0, and enter PM{0 – 2}
WORCTRL |= 0x04;
// Reset Sleep Timer
char temp = WORTIME0;
while(temp == WORTIME0);
temp = WORTIME0;
while(temp == WORTIME0);
WOREVT1 = desired event0 >> 8;
WOREVT0 = desired event0;
PCON |= 0x01;
// Wait until a positive 32 kHz edge
// Wait until a positive 32 kHz edge
// Set EVENT0, high byte
// Set EVENT0, low byte
// Enter PM{0 – 2}
12.8.3 Low Power RC Oscillator and Timing
12.8.4 Sleep Timer Interrupt
When Event occurs,
WORIRQ.EVENT0_FLAGbit will be asserted. If
the corresponding mask bit, EVENT0_MASK, is
set in the WORIRQ register, the CPU interrupt
flag IRCON.STIF will also be asserted in
addition to the interrupt flag in WORIRQ. If
This section applies to using the low power RC
oscillator as clock source for the Sleep Timer.
0
the
The frequency of the low-power RC oscillator,
which can be used as clock source for the
Sleep Timer, varies with temperature and
supply voltage. In order to keep the frequency
as accurate as possible, the RC oscillator will
be calibrated whenever possible, which is
when the high speed crystal oscillator is
running and the chip is in active mode or PM0.
When the chip goes to PM1 or PM2, the RC
oscillator will use the last valid calibration
result. The frequency of the low power RC
oscillator is therefore locked to fref / 750.
IEN0.STIE=1
when
IRCON.STIF
is
asserted, and ST interrupt request will be
generated.
Note: The ST interrupt is blocked when
SLEEP.MODE≠00
12.8.5 Sleep Timer Registers
This section describes the SFRs associated
with the Sleep Timer.
WORTIME0 (0xA5) - Sleep Timer Low Byte
Bit
Field Name
Reset
R/W
Description
7:0
WORTIME[7:0]
0x00
R
8 LSB of the16 bits selected from the 31-bit Sleep Timer according to the
setting of WORCTRL.WOR_RES[1:0]
SWRS055F
Page 124 of 241
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