bq4011/bq4011Y
Write Cycle (T = T
, V
≤ V
≤ V
)
A
OPR CCmin
CC
CCmax
-70/-70N
-100
-150/-150N
-200
Min. Max. Min. Max. Min. Max. Min. Max.
Symbol
tWC
Parameter
Units
ns
Conditions/Notes
Write cycle time
70
55
-
-
100
90
-
-
150
100
-
-
200
150
-
-
Chip enable to
end of write
tCW
ns
(1)
(1)
Address valid to
end of write
tAW
55
0
-
-
80
0
-
-
90
0
-
-
150
0
-
-
ns
ns
Measured from
address valid to
beginning of write. (2)
Ad dr es s s et u p
time
tAS
Measured from
beginning of write to
end of write. (1)
Write pulse
width
tWP
55
5
-
-
-
-
-
-
75
5
-
-
-
-
-
-
90
5
-
-
-
-
-
-
130
5
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Write recovery
time (write
cycle 1)
Measured from WE
going high to end of
write cycle. (3)
tWR1
tWR2
tDW
Write recovery
time (write
cycle 2)
Measured from CE
going high to end of
write cycle. (3)
15
30
0
15
40
0
15
50
0
15
70
0
Measured from first
low-to-high transition
of either CE or WE.
Data valid to end
of write
Measured from WE
going high to end of
write cycle. (4)
Data hold time
(write cycle 1)
tDH1
Measured from CE
going high to end of
write cycle.(4)
Data hold time
(write cycle 2)
tDH2
0
0
0
0
Write enabled to
output in high Z
I/O pins are in output
state. (5)
tWZ
0
5
25
-
0
5
35
-
0
5
50
-
0
5
70
-
ns
ns
Output active
from end of write
I/O pins are in output
state. (5)
tOW
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Aug. 1993 C
6
TI [ TEXAS INSTRUMENTS ]
