bq29330
www.ti.com
SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
CELL–
DBT NO.
RHB NO.
1
28
29
30
4,32
1
Output of scaled value of the measured cell voltage.
Output of scaled value of the measured cell voltage.
Integrated 2.5-V regulator output
Power supply ground
CELL+
REG
2
3
VSS
4, 23
5
XRST
SRN
Active-low output
6
2
Current sense terminal
Current sense positive terminal when charging relative to SRN; current sense negative
terminal when discharging relative to SRN
SRP
VC5
VC4
VC3
VC2
VC1
7
8
3
4
5
6
7
8
Sense voltage input terminal for most negative cell; balance current input for least positive
cell.
Sense voltage input terminal for least positive cell, balance current input for least positive cell,
and return balance current for third most positive cell.
9
Sense voltage input terminal for third most positive cell, balance current input for third most
positive cell, and return balance current for second most positive cell.
10
11
12
Sense voltage input terminal for second most positive cell, balance current input for second
most positive cell, and return balance current for most positive cell.
Sense voltage input terminal for most positive cell, balance current input for most positive cell,
and battery stack measurement input
BAT
13
14
16
17
19
20
21
22
24
25
10
11
13
14
16
17
18
19
21
22
Charge pump, charge N-CH FET gate drive
Charge pump, charge N-CH FET gate drive
Charge pump output, discharge N-CH FET gate drive
PACK positive terminal and alternative power source
Power supply voltage
CHG
DSG
PACK
VCC
ZVCHG
GPOD
PMS
Connect the precharge P-CH FET drive here
NCH FET open-drain output
Determines CHG output state on POR
3.3-V output for LED display power supply
Provides thermistor bias current
LEDOUT
TOUT
Digital input that provides the timing clock for the OC and SC delays and also acts as the
watchdog clock.
WDI
26
23
SCLK
28
29
25
26
Open-drain serial interface clock with internal 10-kΩ pullup to VREG
SDATA
Open-drain bidirectional serial interface data with internal 10-kΩ pullup to VREG
Open-drain output used to indicate status register changes. With internal 100-kΩ
pullup to VREG
XALERT
NC
30
27
15,18,27
9,12,15, 24,31 Not electrically connected to the IC
3
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