SLUS606N – JUNE 2004 – REVISED NOVEMBER 2008
..................................................................................................................................................
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME
bq24100,
bq24108,
bq24109
14
bq24103,
bq24103A
bq24104
14
bq24105
bq24113,
bq24113A
14
bq24115
I/O
DESCRIPTION
BAT
14
14
I
Battery voltage sense input. Bypass it with a 0.1
µF
capacitor to PGND if
there are long
inductive
leads to battery.
Charger enable input. This active low input, if set high, suspends charge
and places the device in the low-power sleep mode. Do not pull up this
input to VTSB.
Available on parts with fixed output voltage. Ground or float for single-cell
operation (4.2 V). For two-cell operation (8.4 V) pull up this pin with a
resistor to V
CC
.
Charge mode selection: low for precharge as set by ISET2 pin and high
(pull up to VTSB or <7 V) for fast charge as set by ISET1.
Output voltage analog feedback adjustment. Connect the output of a
resistive voltage divider powered from the battery terminals to this node to
adjust the output battery voltage regulation.
Charger input voltage.
Charger current set point 1 (fast charge). Use a resistor to ground to set
this value.
Charge current set point 2 (precharge and termination), set by a resistor
connected to ground. A low-level CMODE signal selects the ISET2 charge
rate, but if the battery voltage reaches the regulation set point,
bqSWITCHER changes to voltage regulation regardless of CMODE input.
No connection. This pin must be left floating in the application.
Charge current output inductor connection. Connect a zener TVS diode
between OUT pin and PGND pin to clamp the voltage spike to protect the
power MOSFETs during abnormal conditions.
Power-good status output (open drain). The transistor turns on when a
valid V
CC
is detected. It is turned off in the sleep mode. PG can be used to
drive a LED or communicate with a host processor.
Power ground input
CE
16
16
16
16
16
I
CELLS
13
13
I
CMODE
7
7
I
FB
IN
ISET1
3, 4
8
3, 4
8
13
3, 4
8
3, 4
8
13
3, 4
8
I
I
I/O
ISET2
9
9
9
9
9
I/O
N/C
OUT
13
1
20
5
17,18
15
1
20
5
17,18
15
1
20
5
17,18
15
19
1
20
5
17,18
15
19
1
20
5
17, 18
15
-
O
O
O
PG
PGND
SNS
I
Charge current-sense input. Battery current is sensed via the voltage drop
developed on this pin by an external sense resistor in series with the
battery pack. A 0.1-µF capacitor to PGND is required.
Charge status 1 (open-drain output). When the transistor turns on
indicates charge in process. When it is off and with the condition of STAT2
indicates various charger conditions (See
Charge status 2 (open-drain output). When the transistor turns on
indicates charge is done. When it is off and with the condition of STAT1
indicates various charger conditions (See
Temperature sense input. This input monitors its voltage against an
internal threshold to determine if charging is allowed. Use an NTC
thermistor and a voltage divider powered from VTSB to develop this
voltage. (See
Timer and termination control. Connect a capacitor from this node to GND
to set the bqSWITCHER timer. When this input is low, the timer and
termination detection are disabled.
Analog device input. A 0.1
µF
capacitor to VSS is required.
Analog ground input
TS internal bias regulator voltage. Connect capacitor (with a value
between a 0.1-µF and 1-µF) between this output and VSS.
There is an internal electrical connection between the exposed thermal
pad and VSS. The exposed thermal pad must be connected to the same
potential as the VSS pin on the printed circuit board. The power pad can
be used as a
star
ground connection between V
SS
and PGND. A common
ground plane may be used. VSS pin must be connected to ground at all
times.
STAT1
2
2
2
2
2
O
STAT2
19
19
19
O
TS
12
12
12
12
12
I
TTC
VCC
VSS
VTSB
7
6
10
11
7
6
10
11
7
6
10
11
6
10
11
6
10
11
I
I
O
Exposed
Thermal
Pad
Pad
Pad
Pad
Pad
Pad
6
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s):
TI [ TEXAS INSTRUMENTS ]
