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SLUS694B – MARCH 2006 – REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C
≤
T
J
≤
125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
I
IL
TIMERS
K
(TMR)
R
(TMR) (9)
t
(PRECHG)
I
(FAULT)
Timer set factor
External resistor limits
Precharge timer
Timer fault recovery pullup from
OUT to BAT
t
(CHG)
= K
(TMR)
× R
(TMR)
0.313
30
0.09 × t
(CHG)
0.360
0.414
100
0.10 × t
(CHG)
0.11 × t
(CHG)
1
s/Ω
kΩ
s
kΩ
Low-level input current, Mode
TEST CONDITIONS
MIN
–1
TYP
MAX
UNIT
µA
CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW
→
POWER GOOD)
V
(SLPENT) (10)
Sleep-mode entry threshold
V
(UVLO)
≤
V
I(BAT)
≤
V
O(BAT-REG)
,
No t
(BOOT-UP)
delay
V
(UVLO)
≤
V
I(BAT)
≤
V
O(BAT-REG)
,
No t
(BOOT-UP)
delay
R
(TMR)
= 50 kΩ,
V
(IN)
decreasing below threshold, 100-ns
fall time, 10-mv overdrive
V
VCC
≥
V
I(BAT)
+190 mV
22.5
V
VCC
≤
V
I(BAT)
+125 mV
V
V
(SLPEXIT) (10)
Sleep-mode exit threshold
t
(DEGL)
Deglitch time for sleep mode
(11)
ms
START-UP CONTROL BOOT-UP
t
(BOOT-UP)
Boot-up time
On the first application of input with
Mode Low
120
150
180
ms
SWITCHING POWER SOURCE TIMING
Switching power source from
input to battery
When input applied. Measure from:
[PG: Lo
→
Hi to I
(IN)
> 5 mA],
I
(OUT)
= 100 mA,
R
TRM
= 50 K
T
J
(Q1 and Q3 only)
T
J
(Q1 and Q3 only)
T
J
(Q2)
Decreasing V
CC
115
155
30
135
°C
t
SW-BAT
50
µs
THERMAL SHUTDOWN REGULATION
(12)
T
(SHTDWN)
T
J(REG)
UVLO
V
(UVLO)
Undervoltage lockout
Hysteresis
2.45
2.50
27
2.65
V
mV
Temperature trip
Thermal hysteresis
Temperature regulation limit
(9) To disable the safety timer and charge termination, tie TMR to the V
REF
pin.
(10) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN).
(11) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
(12) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.
6
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