AM6548, AM6528, AM6526
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021
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表6-53. PRU_ICSSG0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
PRU_ICSSG PWM Output A
BALL [4]
[3]
PRG0_PWM2_A0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
W24
V27
PRG0_PWM2_A1
PRU_ICSSG PWM Output A
PRG0_PWM2_A2
PRU_ICSSG PWM Output A
AC27
Y24
PRG0_PWM2_B0
PRU_ICSSG PWM Output B
PRG0_PWM2_B1
PRU_ICSSG PWM Output B
U25
PRG0_PWM2_B2
PRU_ICSSG PWM Output B
AA25
V24
PRG0_PWM3_A0
PRU_ICSSG PWM Output A
PRG0_PWM3_A1
PRU_ICSSG PWM Output A
Y25
PRG0_PWM3_A2
PRU_ICSSG PWM Output A
AA27
W25
U27
PRG0_PWM3_B0
PRU_ICSSG PWM Output B
PRG0_PWM3_B1
PRU_ICSSG PWM Output B
PRG0_PWM3_B2
PRU_ICSSG PWM Output B
V28
PRG0_RGMII1_RXC
PRG0_RGMII1_RX_CTL
PRG0_RGMII1_TXC
PRG0_RGMII1_TX_CTL
PRG0_RGMII2_RXC
PRG0_RGMII2_RX_CTL
PRG0_RGMII2_TXC
PRG0_RGMII2_TX_CTL
PRG0_RGMII1_RD0
PRG0_RGMII1_RD1
PRG0_RGMII1_RD2
PRG0_RGMII1_RD3
PRG0_RGMII1_TD0
PRG0_RGMII1_TD1
PRG0_RGMII1_TD2
PRG0_RGMII1_TD3
PRG0_RGMII2_RD0
PRG0_RGMII2_RD1
PRG0_RGMII2_RD2
PRG0_RGMII2_RD3
PRG0_RGMII2_TD0
PRG0_RGMII2_TD1
PRG0_RGMII2_TD2
PRG0_RGMII2_TD3
PRG0_UART0_CTSn
PRG0_UART0_RTSn
PRG0_UART0_RXD
PRG0_UART0_TXD
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG UART Clear to Send (active low)
PRU_ICSSG UART Request to Send (active low)
PRU_ICSSG UART Receive Data
PRU_ICSSG UART Transmit Data
Y25
I
Y24
IO
O
I
AD28
AB25
AB27
AA25
AC24
AB24
V24
I
IO
O
I
I
W25
W24
AA27
AD27
AC26
AD26
AA24
AB28
AC28
AC27
AB26
AC25
AD25
AD24
AE27
V26
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
O
I
U25
Y28
O
AA28
表6-54. PRU_ICSSG1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
PRU_ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
PRG1_ECAP0_IN_APWM_OUT
IO
AC21
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