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ZCE BALL
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
D7
D8
VDDA_ADC
VDDA_ADC
VDDS
NA
PWR
PWR
D12, F16,
M16, T6, T14 K13, N6, P9,
P14
E6, E14, F9, VDDS
NA
NA
R8, R9, R11, P7, P8
R12, R13
VDDSHV1
VDDSHV1
PWR
NA
NA
P10, P11
P12, P13
H14, J14
VDDSHV2
VDDSHV3
VDDSHV4
VDDSHV2
VDDSHV3
VDDSHV4
NA
NA
NA
PWR
PWR
PWR
G15, H14,
H15
M14, M15,
N15
K14, L14
E10, E11,
VDDSHV5
VDDSHV6
VDDSHV5
VDDSHV6
NA
NA
PWR
PWR
E11, E12,
E13, F14, P6, E12, E13,
R7
F14, G14, N5,
P5, P6
G5, H5, H6,
K4, K5, M5,
M6, N5
E5, F5, G5,
H5, J5, K5, L5
VDDS_DDR
VDDS_DDR
VDDS_OSC
NA
PWR
U10
T8
R11
R10
E7
VDDS_OSC
NA
NA
NA
NA
NA
NA
NA
NA
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
VDDS_PLL_MPU
VDDS_RTC
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
C5
H16
C6
H15
D7
VDDS_PLL_MPU
VDDS_RTC
C10
C12
E9
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDD_CORE
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDD_CORE
D10
F9, F11, G9, F6, F7, G6,
G11, H7, H8, G7, G10,
H12, H13, J7, H11, J12, K6,
J8, J12, J13, K8, K12, L6,
K15, K16, L7, L7, L8, L9,
L8, L12, L13, M11, M13,
M7, M8, M12, N8, N9, N12,
M13, N9,
N13
N11, P9, P11
NA
F10, F11,
F12, F13,
G13, H13,
J13
VDD_MPU
VDD_MPU (26)
NA
PWR
(27)
NA
R5
B9
A2
M5
A9
VDD_MPU_MON
VPP
VDD_MPU_MON
NA
NA
0
A
VPP
PWR
AP
VREFN
VREFN
Z
Z
Z
0
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
NA
NA
NA
Analog
Analog
A9
B9
VREFP
VREFP
0
AP
Z
VDDA_ADC /
VDDA_ADC
Copyright © 2011–2013, Texas Instruments Incorporated
Terminal Description
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