ADS7828-Q1
SBAS456A –DECEMBER 2008–REVISED OCTOBER 2009.......................................................................................................................................... www.ti.com
DEVICE INFORMATION
The ADS7828 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on
capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a
0.6μ CMOS process.
The ADS7828 core is controlled by an internally generated free-running clock. When the ADS7828 is not
performing conversions or being addressed, it keeps the A/D converter core powered off, and the internal clock
does not operate.
The simplified diagram of input and output for the ADS7828 is shown in Figure 2.
2.7 V to 3.6 V
5 W
+
1 µF to
10 µF
ADS7828
2 kW
2 kW
REFIN
/
VDD
+
REFOUT
0.1 µF
1 µF to
10 µF
Microcontroller
CH0
SDA
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SCL
A0
A1
GND
Figure 2. Simplified I/O Diagram
Analog Input
When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal
capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the
sample period, the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has
been fully charged, there is no further input current. The amount of charge transfer from the analog source to the
converter is a function of conversion rate.
Reference
The ADS7828 can operate with an internal 2.5-V reference or an external reference. If a 5-V supply is used, an
external 5-V reference is required in order to provide full dynamic range for a 0 V to +VDD analog input. This
external reference can be as low as 50 mV. When using a 2.7-V supply, the internal 2.5-V reference will provide
full dynamic range for a 0 V to +VDD analog input.
As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is
often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This
means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as
the reference voltage is reduced.
The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5-V reference, the
internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output
code. When the external reference is 50 mV, the potential error contribution from the internal noise is 50 times
larger—16 LSBs. The errors due to the internal noise are Gaussian in nature and can be reduced by averaging
consecutive conversion results.
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