ADS7810
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SBAS014A –MARCH 1992–REVISED SEPTEMBER 2010
PIN ASSIGNMENTS (continued)
PIN
DIGITAL
I/O
DESCRIPTION
NO.
NAME
Data bit 2. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
16
D2
O
O
O
Data bit 1. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
17
18
D1
Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high,
or when R/C is low, or when a conversion is in progress.
D0 (LSB)
19
20
21
22
NC
Not internally connected.
+VANA
+VDIG
DGND
Analog positive supply input. Nominally +5V. Connect directly to pins 21, 27, and 28.
Digital supply input. Nominally +5V. Connect directly to pins 20, 27, and 28.
Digital ground.
Read/Convert input. With CS low, a falling edge on R/C puts the internal sample/hold into
the hold state and starts a conversion. With CS low and no conversion in progress, a
rising edge on R/C enables the output data bits.
23
24
R/C
CS
I
I
Chip select. With R/C low, a falling edge on CS will initiate a conversion. With R/C high
and no conversion in progress, a falling edge on CS will enable the output data bits.
Busy output. Falls when a conversion is started, and remains low until the conversion is
completed and the data are latched into the output register. With CS low and R/C high,
output data will be valid when BUSY rises, so that the rising edge can be used to latch
the data.
25
BUSY
O
Analog negative supply input. Nominally –5V. Decouple to ground with 0.1mF ceramic
and 10vF tantalum capacitors.
26
27
28
–VANA
+VDIG
+VANA
Digital supply input. Nominally +5V. Connect directly to pins 20, 21, and 28.
Analog positive supply input. Nominally +5V. Connect directly to pins 20, 21, and 27, and
decouple to ground with 0.1mF ceramic and 10mF tantalum capacitors.
Copyright © 1992–2010, Texas Instruments Incorporated
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