ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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6.6 Timing Requirements
over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
MIN
MAX
UNIT
1.65 V ≤DVDD ≤2.0 V
tw(CLH)
tw(CLL)
tc(SC)
Pulse duration, CLKIN high
49
49
64
32
32
16
10
20
5
ns
ns
Pulse duration, CLKIN low
SCLK period
ns
tw(SCL)
tw(SCH)
td(CSSC)
td(SCCS)
tw(CSH)
tsu(DI)
Pulse duration, SCLK low
ns
Pulse duration, SCLK high
ns
Delay time, first SCLK rising edge after CS falling edge
Delay time, CS rising edge after final SCLK falling edge
Pulse duration, CS high
ns
ns
ns
Setup time, DIN valid before SCLK falling egde
Hold time, DIN valid after SCLK falling edge
Pulse duration, SYNC/RESET low to generate device reset
Pulse duration, SYNC/RESET low for synchronization
Setup time, SYNC/RESET valid before CLKIN rising edge
ns
th(DI)
8
ns
tw(RSL)
tw(SYL)
tsu(SY)
2048
1
tCLKIN
tCLKIN
ns
2047
10
2.7 V ≤DVDD ≤3.6 V
tw(CLL)
tw(CLH)
tc(SC)
Pulse duration, CLKIN low
49
49
40
20
20
16
10
15
5
ns
ns
Pulse duration, CLKIN high
SCLK period
ns
tw(SCL)
tw(SCH)
td(CSSC)
td(SCCS)
tw(CSH)
tsu(DI)
Pulse duration, SCLK low
ns
Pulse duration, SCLK high
ns
Delay time, first SCLK rising edge after CS falling edge
Delay time, CS rising edge after final SCLK falling edge
Pulse duration, CS high
ns
ns
ns
Setup time, DIN valid before SCLK falling egde
Hold time, DIN valid after SCLK falling edge
Pulse duration, SYNC/RESET low to generate device reset
Pulse duration, SYNC/RESET low for synchronization
Setup time, SYNC/RESET valid before CLKIN rising edge
ns
th(DI)
8
ns
tw(RSL)
tw(SYL)
tsu(SY)
2048
1
tCLKIN
tCLKIN
ns
2047
10
6.7 Switching Characteristics
over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.65 V ≤DVDD ≤2.0 V
Propagation delay time, CS falling edge to
DOUT driven
tp(CSDO)
tp(SCDO)
tp(CSDOZ)
50
32
75
ns
ns
ns
Progapation delay time, SCLK rising edge to
valid new DOUT
Propagation delay time, CS rising edge to DOUT
high impedance
tw(DRH)
tw(DRL)
Pulse duration, DRDY high
Pulse duration, DRDY low
SPI timeout
4
4
tCLKIN
tCLKIN
tCLKIN
32768
Measured from supplies at
90% to first DRDY rising
edge
tPOR
Power-on-reset time
250
5
µs
µs
tREGACQ Register default acquisition time
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