ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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6.8 Timing Diagrams
tw(CLH)
tw(CLL)
CLKIN
tw(DRL)
DRDY
tw(DRH)
CS
SCLK
DIN
tw(SCL)
td(SCCS)
td(CSSC)
tc(SC)
tw(CSH)
tw(SCH)
tsu(DI)
th(DI)
tp(CSDO)
MSB
tp(SCDO)
tw(CSDOZ)
LSB
MSB - 1
LSB + 1
DOUT
NOTE: SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low.
图6-1. SPI Timing Diagram
CLKIN
tsu(SY)
tw(SYL)
tw(RSL)
SYNC/RESET
图6-2. SYNC/RESET Timing Requirements
90%
Supplies
tPOR
DRDY
图6-3. Power-On-Reset Timing
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