ADS1291
ADS1292
ADS1292R
SBAS502A –DECEMBER 2011–REVISED MARCH 2012
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// Follow Power-Up Sequencing
Analog/Digital Power-Up
Set CLKSEL Pin = 0 and
Provide External Clock
fCLK = 512 kHz
Yes
External
Clock
No
Set CLKSEL Pin = 1
and Wait for Oscillator
to Wake Up
// If START is Tied High, After This Step
// DRDY Toggles at fMOD/256
Set PWDN/RESET = 1
Wait for 1 s for
// Delay for Power-On Reset and Oscillator Start-Up
Power-On Reset
// Activate DUT
Issue Reset Pulse,
Wait for 18 tCLKs
//CS can be Either Tied Permanently Low
// Or Selectively Pulled Low Before Sending
// Commands or Reading/Sending Data From/To Device
// Device Wakes Up in RDATAC Mode, so Send
// SDATAC Command so Registers can be Written
SDATAC
Send SDATAC
Command
No
Set PDB_REFBUF = 1
and Wait for Internal
Reference To Settle
// If Using Internal Reference, Send This Command
-- WREG CONFIG2 A0h
External Reference
Yes
// DRATE = 500 SPS
Write Certain Registers,
Including Input Short
WREG CONFIG1 02h
// Set All Channels to Input Short
WREG CHnSET 01h
// Activate Conversion
Set START = 1
RDATAC
// After This Point DRDY Should Toggle at
// fCLK Review
// Put the Device Back in RDATAC Mode
RDATAC
Capture Data and
Check Noise
// Look for DRDY and Issue 24 + n 24 SCLKs
// Activate a (1 mV VREF/2.4) Square-Wave Test Signal
// On All Channels
SDATAC
WREG CONFIG2 A3h
WREG CHnSET 05h
RDATAC
Set Test Signals
Capture Data and
Test Signals
// Look for DRDY and Issue 24 + n 24 SCLKs
Figure 63. Initial Flow at Power-Up
62
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