ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Crosstalk
f = 1kHz, –0.5dBFS(5)
–107
106
110
111
106
107
–108
109
dB
dB
dB
dB
dB
dB
dB
dB
dB
Hz
Hz
dB
High-Speed mode
101
103
VREF = 2.5V
VREF = 3V
Signal-to-noise ratio (SNR)(6)
(unweighted)
High-Resolution mode
Low-Power mode
Low-Speed mode
101
101
Total harmonic distortion (THD)(7)
Spurious-free dynamic range
Passband ripple
VIN = 1kHz, –0.5dBFS
–96
±0.005
Passband
0.453 fDATA
0.49 fDATA
–3dB Bandwidth
High-Resolution mode
All other modes
95
100
Stop band attenuation
Stop band
High-Resolution mode
All other modes
0.547 fDATA
0.547 fDATA
127.453 fDATA
63.453 fDATA
Hz
Hz
s
High-Resolution mode
All other modes
39/fDATA
38/fDATA
78/fDATA
76/fDATA
Group delay
s
High-Resolution mode
All other modes
Complete settling
Complete settling
s
Settling time (latency)
s
VOLTAGE REFERENCE INPUTS
Negative reference input (VREFN)
AGND – 0.1
AGND + 0.1
V
0.1 ≤ fCLK ≤ 27MHz
27 < fCLK ≤ 32.768MHz
32.768MHz < fCLK ≤ 37MHz
0.5
0.5
0.5
2.5
2.5
3.1
2.6
2.1
V
(8)
Reference input voltage (VREF
(VREF = VREFP – VREFN)
)
V
2.048
1.3
V
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
1.3
ADS1274
Reference Input impedance
2.6
13
0.65
0.65
1.3
ADS1278
Reference Input impedance
6.5
DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)
VIH
0.7 IOVDD
DGND
IOVDD
0.3 IOVDD
IOVDD
0.2 IOVDD
±10
V
V
VIL
VOH
IOH = 4mA
IOL = 4mA
0.8 IOVDD
DGND
V
VOL
V
Input leakage
0 < VIN DIGITAL < IOVDD
High-Speed mode(8)
Other modes
μA
MHz
MHz
0.1
0.1
37
Master clock rate (fCLK
)
27
(5) Worst-case channel crosstalk between one or more channels.
(6) Minimum SNR is ensured by the limit of the DC noise specification.
(7) THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
(8) fCLK = 37MHz max for High-Speed mode, and 27MHz max for all other modes. See Table 7 for VREF restrictions in High-Speed mode.
4
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