ADC0801, ADC0802
ADC0803, ADC0804, ADC0805
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SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013
TYPICAL CHARACTERISTICS
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Logic Input Threshold Voltage vs
Supply Voltage
Delay From Falling Edge of RD to Output
Data Valid vs Load Capacitance
Figure 1.
Figure 2.
CLK IN Schmitt Trip Levels vs
Supply Voltage
fCLK vs Clock Capacitor
Figure 3.
Figure 4.
Full-Scale Error vs
Conversion Time
Effect of Unadjusted Offset Error
VREF/2 Voltage
Figure 5.
Figure 6.
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