ADC0801, ADC0802
ADC0803, ADC0804, ADC0805
SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013
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AC ELECTRICAL CHARACTERISTICS
The following specifications apply for VCC=5 VDC and TMIN≤ TA≤TMAX (unless otherwise specified)
PARAMETER
CONDITIONS
fCLK = 640 kHz(1)
MIN
103
66
TYP
MAX UNITS
114
µs
TC
Conversion Time
(2)(1)
See
73 1/fCLK
Clock Frequency
Clock Duty Cycle
100
40%
640
1460
kHz
fCLK
VCC = 5V(2)
60%
INTR tied to WR with CS = 0 VDC,
fCLK = 640 kHz
CR
Conversion Rate in Free-Running Mode
Width of WR Input (Start Pulse Width)
8770
100
9708
conv/s
ns
(3)
tW(WR)L
tACC
CS = 0 VDC
Access Time (Delay from Falling Edge of RD
to Output Data Valid)
CL = 100 pF
135
125
300
200
200
450
ns
TRI-STATE Control (Delay from Rising Edge of CL = 10 pF, RL = 10k (See TRI-STATE
t1H, t0H
tWI, tRI
ns
ns
RD to Hi-Z State)
TEST CIRCUITS AND WAVEFORMS)
Delay from Falling Edge of WR or RD to Reset
of INTR
CIN
Input Capacitance of Logic Control Inputs
5
5
7.5
7.5
pF
pF
COUT
TRI-STATE Output Capacitance (Data Buffers)
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1)
VIN (0)
IIN (1)
IIN (0)
Logical “1” Input Voltage (Except Pin 4 CLK IN) VCC = 5.25 VDC
Logical “0” Input Voltage (Except Pin 4 CLK IN) VCC = 4.75 VDC
2
15
0.8
1
VDC
VDC
Logical “1” Input Current (All Inputs)
Logical “0” Input Current (All Inputs)
VIN = 5 VDC
VIN = 0 VDC
0.005
–1 –0.005
µADC
µADC
CLOCK IN AND CLOCK R
CLK IN (Pin 4) Positive Going Threshold
Voltage
VT+
2.7
3.1
3.5
2.1
VDC
VDC
CLK IN (Pin 4) Negative Going Threshold
Voltage
VT−
1.5
0.6
1.8
1.3
VH
CLK IN (Pin 4) Hysteresis (VT+)–(VT−)
2
VDC
VDC
VDC
VOUT (0) Logical “0” CLK R Output Voltage
VOUT (1) Logical “1” CLK R Output Voltage
DATA OUTPUTS AND INTR
Logical “0” Output Voltage
IO = 360 µA, VCC = 4.75 VDC
0.4
IO = −360 µA, VCC = 4.75 VDC
2.4
VOUT (0) Data Outputs
IOUT = 1.6 mA, VCC = 4.75 VDC
IOUT = 1.0 mA, VCC = 4.75 VDC
IO = −360 µA, VCC = 4.75 VDC
IO = −10 µA, VCC = 4.75 VDC
VOUT = 0 VDC
0.4
0.4
VDC
VDC
INTR Output
2.4
4.5
–3
VDC
VOUT (1) Logical “1” Output Voltage
VDC
µADC
µADC
mADC
mADC
TRI-STATE Disabled Output Leakage (All Data
Buffers)
IOUT
VOUT = 5 VDC
3
ISOURCE
ISINK
POWER SUPPLY
Supply Current (Includes Ladder Current)
VOUT Short to GND, TA = 2 5°C
VOUT Short to VCC, TA = 25°C
4.5
9
6
16
fCLK = 640 kHz, VREF/2 = NC,
TA = 25°C and CS = 5 V
ICC
ADC0801/02/03/04LCJ/05
ADC0804LCN/LCWM
1.1
1.9
1.8
2.5
mA
mA
(1) Accuracy is specified at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle
limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
(2) With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the
conversion process. The start request is internally latched, see Figure 48 and FUNCTIONAL DESCRIPTION.
(3) The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide
pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse
(see TIMING DIAGRAMS).
4
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