SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 AND 54S/74S DEVICES
V
CC
Test
R
L
V
CC
Point
Test
S1
Point
V
CC
From Output
Under Test
(see
Note B)
R
L
R
L
C
L
From Output
Under Test
1 kΩ
(see Note B)
(see Note A)
From Output
Under Test
Test
Point
C
L
(see Note A)
C
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
0 V
High-Level
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
Pulse
t
w
t
t
su
h
3 V
Data
Input
Low-Level
Pulse
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
Control
(low-level
enabling)
1.5 V
1.5 V
0 V
3 V
0 V
1.5 V
1.5 V
Input
t
t
t
t
PZL
PLZ
≈1.5 V
t
PHL
PLH
Waveform 1
(see Notes C
and D)
1.5 V
In-Phase
Output
(see Note D)
V
OH
OL
V
OL
V
OL
+ 0.5 V
1.5 V
1.5 V
1.5 V
V
t
PZH
PHZ
t
t
PHL
PLH
V
OH
V
OH
Out-of-Phase
Output
V
Waveform 2
(see Notes C
and D)
OH
OL
– 0.5 V
1.5 V
1.5 V
(see Note D)
V
≈1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t
.
PLH PHL PHZ
PZL
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t and t ≤ 7 ns for Series
O
r
f
54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.
r
f
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
9
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