TL284xB, TL384xB
HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS
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SLVS610A–AUGUST 2006–REVISED SEPTEMBER 2006
APPLICATION INFORMATION (continued)
Shutdown Technique
The PWM controller (see Figure 5) can be shut down by two methods: either raise the voltage at ISENSE above
1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output
of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output
remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed.
In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling
VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset.
1 kΩ
V
REF
COMP
Shutdown
I
330 Ω
SENSE
500 Ω
Shutdown
To Current-Sense
Resistor
Figure 5. Shutdown Techniques
A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope
compensation for converters requiring duty cycles over 50% (see Figure 6). Note that capacitor C forms a filter
with R2 to suppress the leading-edge switch spikes.
V
REF
0.1 µF
R
T
R /C
T
T
C
T
R1
I
SENSE
R2
I
SENSE
C
R
SENSE
Figure 6. Slope Compensation
13
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