THC63LVD1023B_Rev.3.0_E
Switching Characteristics
V
CC
= VCC=PVCC=LVCC
Symbol
t
TCIP
t
TCH
t
TCL
t
TS
t
TH
t
TCD
t
TCOP
t
LVT
t
TOP1
t
TOP0
t
TOP6
t
TOP5
t
TOP4
t
TOP3
t
TOP2
t
TPLL
t
DEINT
Parameter
CLK IN Period(Fig4,5)
CLK IN High Time(Fig4,5)
CLK IN Low Time(Fig4,5)
TTL Data Setup to CLK IN(Fig4,5)
TTL Data Hold from CKL IN(Fig4,5)
CLK IN to TCLK+/- Delay(Fig4,5)
MODE<1:0>=LL
Dual-in/Dual-out
CLK OUT Period(Fig6)
LVDS Transition Time(Fig2)
Output Data
Position0 (Fig6)
Output Data
Position1 (Fig6)
Output Data
Position2 (Fig6)
Output Data
Position3 (Fig6)
Output Data
Position4 (Fig6)
Output Data
Position5 (Fig6)
Output Data
Position6 (Fig6)
PLL Lock time(Fig3)
DE input period (Fig3-1)
Single-in / Dual-out, DDR Off mode
only(MODE<2:0>=LHL)
DE High time (Fig3-1)
t
DEH
Single-in / Dual-out, DDR Off mode
only(MODE<2:0>=LHL)
DE Low time(Fig3-1)
t
DEL
Single-in / Dual-out, DDR Off mode
only(MODE<2:0>=LHL)
2t
TCIP
ns
2t
TCIP
tTCIP*(2m)
a
ns
4t
TCIP
tTCIP*(2n)
a
ns
t
TCOP
=
6.25ns~20ns
-0.15
t
TCOP
---------------
–
0.15
7
t
TCOP
2 ---------------
–
0.15
7
t
TCOP
3 ---------------
–
0.15
7
t
TCOP
4 ---------------
–
0.15
7
t
TCOP
5 ---------------
–
0.15
7
t
TCOP
6 ---------------
–
0.15
7
t
TCOP
---------------
7
t
TCOP
2 ---------------
7
t
TCOP
3 ---------------
7
t
TCOP
4 ---------------
7
t
TCOP
5 ---------------
7
t
TCOP
6 ---------------
7
Min.
6.25
0.35t
TCIP
0.35t
TCIP
2.5
0.0
(4+3/7)t
TCIP
+2.6
Typ.
0.5t
TCIP
0.5t
TCIP
Max.
100
0.65t
TCIP
0.65t
TCIP
Units
ns
ns
ns
ns
ns
(4+3/7)t
TCIP
+7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
6.25
0.6
0.0
50
1.5
+0.15
t
TCOP
--------------- + 0.15
7
t
TCOP
2 --------------- + 0.15
7
t
TCOP
3 --------------- + 0.15
7
t
TCOP
4 --------------- + 0.15
7
t
TCOP
5 --------------- + 0.15
7
t
TCOP
6 --------------- + 0.15
7
10.0
a. Refer to Fig3-1 for details.
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
