THC63LVD1023B_Rev.3.0_E
AC Timing Diagrams (Continued)
RS pin
VIHM
VOD
VREF
VCC/2
350mV
200mV
VIMM
VILM
Input Voltage of RS pin
VCC/2
tTCIP
tTCH
VREF
tTCL
VREF
VCC
GND
CLKINx
x=1,2
VREF
tTS
Current Data
tTH
Rxn, Gxn, Bxn
HSYNCx
VCC
GND
VSYNCx
VREF
VREF
DEx
CONTx1
CONTx2
t
TCD
x=1,2 n=0-9
TCLKx+/-
x=1,2
VOD
VOC
Txy+/-
x=1,2
y= A, B, C, D, E
Current Data
Note:
CLKINx: for R/F=GND, denote as solid line,
for R/F=VCC, denote as dashed line.
Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing
x=1,2
RS pin
VIHM
VOD
VREF
VCC/2
350mV
200mV
tTCIP
VIMM
VILM
Input Voltage of RS pin
VCC/2
tTCH
VREF
tTS
tTCL
VREF
tTS
VCC
GND
CLKINx
x=1,2
VREF
tTH
tTH
Rxn, Gxn, Bxn
HSYNCx
VSYNCx
DEx
CONTx1
VCC
GND
1st Pixel
Data
2nd Pixel
Data
VREF
VREF
CONTx2
t
TCD
x=1,2 n=0-9
TCLKx+/-
x=1,2
VOD
VOC
Txy+/-
x=1,2
y= A, B, C, D, E
Current Data
Note:
CLKINx: for R/F=GND, denote as solid line,
x=1,2
for R/F=VCC, denote as dashed line.
Fig5. CLKIN Period, High/Low Time, Setup/Hold Timing for Double Edge Input Mode (DDR)
MODE<1:0>=HL, MODE2=H
Copyright©2011 THine Electronics, Inc.
11/26
THine Electronics, Inc.
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