THC63LVD1023B_Rev.3.0_E
THC63LVD1023B
160MHz 67Bits LVDS Transmitter
General Description
The THC63LVD1023B transmitter is designed to suport
Single Link transmission between Host and Flat Panel
Display up to 1080p(60Hz) resolutions and Dual Link
transmission between Host and Flat Panel Display up to
1080p(120Hz).
The THC63LVD1023B converts 67bits of CMOS/TTL
data into LVDS (Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin,
and support double edge inputs.
In Dual Link, the transmit clock frequency of 160MHz,
67bits of RGB data are transmitted at an effective rate
of 1.12Gbps per LVDS channel.
In Asynchronous mode, the THC63LVD1023B has 2
independent 35Bits Transmitter.
Features
•
Wide dot clock range suited for TV Signal (480i-
1080p), PC Signal (VGA-QXGA)
TTL/CMOS Input: 10-160MHz
LVDS Output: 20-160MHz
•
PLL requires No external components
•
Flexible Input/Output mode
1. Single/Dual TTL IN, Single/Dual LVDS OUT
2. Double edge input for Single TTL IN/Dual LVDS OUT
3. Input port SW for Single TTL IN/Dual LVDS OUT
4. Asynchronous
Dual TTL IN/Dual LVDS OUT
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Clock edge selectable
3 LVDS data mapping for simplifying PCB layout.
Pseudo Random pattern generation circuit
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
Backward compatible with THC63LVD1023
144pin LQFP
Block Diagram
DATA Port1
32
35
PARALLEL TO SERIAL
5) Input Port SW
6) Crosspoint
R1[9:0]
G1[9:0]
B1[9:0]
CONT1[2:1]
R2[9:0]
G2[9:0]
B2[9:0]
CONT2[2:1]
Hsync1
Vsync1
DE1
Hsync2
Vsync2
DE2
TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TE1 +/-
LVDS OUTPUT
Port1
DATA Port2
Data Formatter
32
6
1) DEMUX
2) MUX
3) Distribution
4) DDR
R/F
RS
MAP
MODE[3:0]
/PDWN
PRBS
ASYNC
35
PARALLEL TO SERIAL
TA2 +/-
TB2 +/-
TC2 +/-
TD2 +/-
TE2 +/-
LVDS OUTPUT
Port2
TCLK1 +/-
CLKIN1
CLKIN2
MUX
PLL
TCLK2 +/-
(20 to 160MHz)
TRANSMITTER CLOCK IN
(10 to 160MHz)
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.