78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
MR17: Interrupt Control/Status Register (continued)
BIT
SYMBOL
TYPE DEFAULT DESCRIPTION
17.3
LP-ACK_INT
RC
0
Link Partner Acknowledge Interrupt: This bit is set high by the
auto-negotiation logic when FLP bursts are received with the
acknowledge bit set.
17.2
17.1
17.0
LS-CHG_INT
RFAULT_INT
RC
RC
RC
0
0
0
Link Status Change Interrupt: This bit is set when the link
transitions from an OK status to a FAIL status.
Remote Fault Interrupt: This bit is set when a remote fault
condition has been indicated by the link partner.
ANEG-
Auto-Negotiation Complete Interrupt: This bit is set by the auto-
negotiation logic upon successful completion of auto-negotiation.
COMP_INT
MR18: Diagnostic Register
BIT
18.15:13
18.12
SYMBOL TYPE DEFAULT DESCRIPTION
RSVD
R
0
0
Reserved
ANEGF
RC
Auto-Negotiation Fail Indication:
This bit is set when auto-
negotiation completes and no common technology was found. It
remains set until read.
18.11
18.10
18.9
DPLX
RATE
RXSD
R
R
R
0
0
0
Duplex Indication: This bit indicates the result of the auto-
negotiation for duplex arbitration as follows:
0 : Half-duplex was the highest common denominator
1 : Full-duplex was the highest common denominator
Rate Indication: This bit indicates the result of the auto-negotiation
for data rate arbitration as follows:
0 : 10Base-T was the highest common denominator
1 : 100Base-TX was the highest common denominator
Receiver Signal Detect Indication: In 10Base-T mode, this bit
indicates that Manchester data has been detected. In 100Base-TX
mode, it indicates that the receive signal activity has been detected
(but not necessarily locked on to).
18.8
RX_LOCK
RSVD
R
R
0
Receive PLL Lock Indication: Indicates that the Receive PLL has
locked onto the receive signal for the selected speed of operation
(10Base-T or 100Base-TX).
18.7:0
00h
Reserved: Must set to ‘00h’.
Page: 19 of 42
© 2009 Teridian Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
