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78Q2133/F 参数 Datasheet PDF下载

78Q2133/F图片预览
型号: 78Q2133/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10 / 100BASE -TX收发器 [10/100BASE-TX Transceiver]
分类和应用: 网络接口电信集成电路电信电路局域网(LAN)标准以太网:16GBASE-T
文件页数/大小: 42 页 / 730 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78Q2123/78Q2133 MicroPHY™  
10/100BASE-TX Transceiver  
MR4: Auto-Negotiation Advertisement Register  
BIT  
SYMBOL TYPE DEFAULT DESCRIPTION  
4.15  
NP  
RSVD  
RF  
R
R
0
0
0
Next Page: Not supported. Reads logic zero.  
4.14  
4.13  
Reserved  
R/W  
Remote Fault: Setting this bit to ‘1’ allows the device to indicate to the  
link partner a Remote Fault Condition.  
4.12  
4.11  
A7  
A6  
R
0
0
Reserved.  
R/W  
Asymmetric PAUSE Support Indication for Full Duplex Links. Default is  
0 indicating not supported. If the MAC supports Asymmetric PAUSE,  
this bit can be written as 1. Writing to this register has no effect until  
auto-negotiation is re-initiated.  
4.10  
A5  
R
0
PAUSE Support Indication for Full Duplex Links. Default is 0 indicating  
not supported. If the MAC supports PAUSE, this bit can be written as 1.  
Writing to this register has no effect until auto-negotiation is re-initiated  
4.9  
4.8  
A4  
A3  
R
0
100BASE-T4: The 78Q2123/78Q2133 do not support 100BASE-T4  
operation.  
R/W  
(1)  
100BASE-TX Full Duplex: If the MR1.14 bit is ‘1’, this bit will be set to  
‘1’ upon reset and will be writeable. Otherwise, this bit cannot be set to  
‘1’ by the management.  
4.7  
4.6  
A2  
A1  
R/W  
R/W  
R/W  
R
(1)  
(1)  
100BASE-TX: If the MR1.13 bit is ‘1’, this bit will be set to ‘1’ upon  
reset and will be writeable. Otherwise, this bit cannot be set to ‘1’ by  
the management.  
10BASE-T Full Duplex: If the MR1.12 bit is ‘1’, this bit will be set to ‘1’  
upon reset and will be writeable. Otherwise, this bit cannot be set to ‘1’  
by the management.  
4.5  
A0  
(1)  
10BASE-T: If the MR1.11 bit is ‘1’, this bit will be set to ‘1’ upon reset  
and will be writeable. Otherwise, this bit cannot be set to ‘1’ by the  
management.  
4.4:0  
S4:0  
01h  
Selector Field: Hard coded with the value of ‘00001’ for IEEE 802.3.  
Note: Technology Ability Field: MR4.12:5 are the Technology Ability Field bits (A7:0). The default value of this  
field is dependent upon the MR1.15:11 register bits. This field can be overwritten by management to auto-  
negotiate to an alternate common technology. Writing to this register has no effect until auto-negotiation is re-  
initiated.  
Page: 15 of 42  
© 2009 Teridian Semiconductor Corporation  
Rev 1.5  
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