78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
MR16: Vendor Specific Register
BIT
16.15
SYMBOL TYPE DEFAULT DESCRIPTION
RPTR
R/W
(0)
Repeater Mode: When set, the 78Q2123/78Q2133 are put into
Repeater mode of operation. In this mode, full duplex is prohibited,
CRS responds to receive activity only and, in 10Base-T mode, the SQE
test function is disabled.
16.14
INPOL
R/W
0
When this bit is ‘0’, the INTR pin is forced low to signal an interrupt.
Setting this bit to ‘1’ causes the INTR pin to be forced high to signal an
interrupt.
16.13
16.12
RSVD
R
0
0
Reserved
TXHIM
R/W
Transmitter High-Impedance Mode: When set, the TXOP/TXON
transmit pins and the TX_CLK pin are put into a high-impedance state.
The receive circuitry remains fully functional.
16.11
16.10
SQEI
NL10
R/W
R/W
0
0
SQE Test Inhibit: Setting this bit to ‘1’ disables 10Base-T SQE testing.
By default, this bit is ‘0’ and the SQE test is performed by generating a
COL pulse following the completion of a packet transmission.
10Base-T Natural Loopback: Setting this bit to ‘1’ causes transmit data
received on the TXD0-3 pins to be automatically looped back to the
RXD0-3 pins when 10Base-T mode is enabled.
16.9
16.8
16.7
16.6
16.5
RSVD
RSVD
RSVD
RSVD
APOL
R
R
0
1
0
1
0
Reserved
Reserved
Reserved
Reserved
R
R
R/W
Auto Polarity: During auto-negotiation and 10BASE-T mode, the
78Q2123/78Q2133 are able to automatically invert the received signal
due to a wrong polarity connection. It does so by detecting the polarity
of the link pulses. Setting this bit to ‘1’ disables this feature.
16.4 RVSPOL
R/W
R/W
0
Reverse Polarity: The reverse polarity is detected either through 8
inverted 10Base-T link pulses (NLP) or through one burst of inverted
clock pulses in the auto-negotiation link pulses (FLP). When the
reverse polarity is detected and if the Auto Polarity feature is enabled,
the 78Q2123/78Q2133 will invert the receive data input and set this bit
to ‘1’. If Auto Polarity is disabled, then this bit is writeable. Writing a ‘1’
to this bit forces the polarity of the receive signal to be reversed.
16.3:2
RSVD
0h
Reserved: Must set to ‘00’.
Page: 17 of 42
© 2009 Teridian Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
