78Q2123/78Q2133
MicroPHY™
10/100BASE-TX Transceiver
Polarity Correction
The 78Q2123/78Q2133 are capable of either automatic or
manual polarity reversal for 10BASE-T and auto-
negotiation functions. Register bits MR16.5 and MR16.4
control this feature. The default is
automatic mode
where MR16.5 is low and MR16.4 indicates if the
detection circuitry has inverted the input signal. To
enter manual mode, MR16.5 should be set high and
MR16.4 will then control the signal polarity.
SQE TEST
The 78Q2123/78Q2133 support the Signal Quality
Error (SQE) function detailed in IEEE-802.3. At an
interval of 1µs after each negative transition of the
TX_EN pin in 10BASE-T mode, the COL pin will go
high for a period of 1µs. SQE is not signalled during
transmission after collision is detected. SQE is
automatically disabled when repeater mode is
enabled. This function can be disabled through
register bit MR16.11.
Natural Loopback
When enabled, whenever the 78Q2123/78Q2133
are transmitting and not receiving on the twisted pair
media (10BASE-T Half Duplex mode), data on the
TXD3-0 pins are looped back onto the RXD3-0 pins.
During a collision, data from the RXI pins is routed to
the RXD3-0 pins. The natural loopback function is
enabled through register bit MR16.10. This feature
is off by default.
Repeater Mode
When register bit MR16.15 is set, the
78Q2123/78Q2133 are placed in repeater mode. In
this mode, full duplex operation is prohibited, CRS
responds only to receive activity and, in 10BASE-T
mode, the SQE test function is disabled.
AUTO-NEGOTIATION
The 78Q2123/78Q2133 support the auto-negotiation
functions of Clause 28 of IEEE-802.3 for 10/100
Mbps operation over copper wiring. This function
can be enabled via register settings. The auto-
negotiation function defaults to ON and bit MR0.12
(ANEGEN) is high after reset. Software can disable
the auto-negotiation function by writing to bit
MR0.12.
The contents of register MR4 are sent to the
78Q2123/78Q2133’s link partner during auto-
negotiation via fast link pulse coding.
4.7/1.13
4.6/1.12
4.5/1.11
The default values of the auto-negotiation registers
are set as follows:
REGISTER.BITS
0.13
0.12
0.8
4.8/1.14
FUNCTION
Speed Select
AN Enable
Duplex
100BASE-TX
Full Duplex
100 BASE-TX
10 BASE-T
Full Duplex
10 BASE-T
DEFAULT VALUE
1 (100 BASE TX)
1 (enabled)
1 (full duplex)
1
1
1
1
These default values can be changed by writing
different values to the registers, then restarting auto-
negotiation.
With
auto-negotiation
enabled,
the
78Q2123/78Q2133 will start sending fast link pulses
at power on, loss of link or upon a command to
restart. At the same time, it will look for either
10BASE-T idle, 100BASE-TX idle, or fast link pulses
from its link partner. If either idle pattern is detected,
the 78Q2123/78Q2133 configure themselves in half-
duplex mode at the appropriate speed. If it detects
fast link pulses, it decodes and analyzes the link
code transmitted by the link partner. When three
identical link code words are received (ignoring the
acknowledge bit) the link code word is stored in
register MR5. Upon receiving three more identical
link code words, with the acknowledge bit set, the
78Q2123/78Q2133 configure themselves to the
highest priority technology common to the two link
partners.
The technology priorities are, in
descending order:
100BASE-TX, Full Duplex
100BASE-TX, Half Duplex
10BASE-T, Full Duplex
10BASE-T, Half Duplex
Once auto-negotiation is complete, register bits
MR18.11:10 will reflect the actual speed and duplex
that was chosen.
If auto-negotiation fails to establish a link for any
reason, register bit MR18.12 will reflect this and auto
negotiation will restart from the beginning. Writing a
‘1’ to bit MR0.9 (RANEG) will also cause auto-
negotiation to restart.
Page: 4 of 42
©
2009 Teridian Semiconductor Corporation
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
