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78Q2120C 参数 Datasheet PDF下载

78Q2120C图片预览
型号: 78Q2120C
PDF下载: 下载PDF文件 查看货源
内容描述: 10 / 100BASE -TX收发器 [10/100BASE-TX Transceiver]
分类和应用: 局域网(LAN)标准
文件页数/大小: 35 页 / 589 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78Q2120C  
10/100BASE-TX  
Transceiver  
REGISTER DESCRIPTION  
The 78Q2120C implements 11 16-bit registers, which are accessible via the MDIO and MDC pins. The supported  
registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the  
MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those  
which are unique to the 78Q2120C, will respond to the broadcast PHYAD value of ‘00000’. The registers specific  
to the 78Q2120C occupy address space MR16-22.  
ADDRESS  
SYMBOL  
MR0  
NAME  
DEFAULT (HEX)  
(3100)  
(7809)  
000E  
0
1
Control  
MR1  
Status  
2
MR2  
PHY Identifier 1  
3
MR3  
PHY Identifier 2  
70C9  
4
MR4  
Auto-Negotiation Advertisement  
Auto-Negotiation Link Partner Ability  
Auto-Negotiation Expansion  
Not Implemented  
Reserved  
(01E1)  
0000  
5
MR5  
6
MR6  
0000  
7
MR7  
0000  
8-14  
15  
16  
17  
18  
19  
20-22  
MR8-14  
MR15  
MR16  
MR17  
MR18  
MR19  
0000  
Not Implemented  
Vendor Specific  
Interrupt Control/Status Register  
Diagnostic Register  
Transceiver Control  
0000  
(0140)  
0000  
0000  
4XXX  
0000  
MR20-MR22 Reserved  
Legend:  
TYPE DESCRIPTION  
TYPE DESCRIPTION  
R
Readable by management.  
Writeable by management. Self  
Clearing.  
W
Writeable by management.  
Readable by management.  
SC  
RC  
Cleared upon a read operation.  
0/1  
Default value upon power up or  
reset.  
(0/1) Default value dependent on pin  
settings. The value in bracket  
indicates typical case.  
Page: 10 of 35  
© 2009 Teridian Semiconductor Corporation  
Rev 1.3