78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
PIN DESCRIPTION (CONTINUED)
REFERENCE AND STATUS PINS
Note: The LOSx, LOLx, and INTxXxB pins are configurable at final test (default open-drain outputs). If CMOS
level outputs are required, please refer to alternate 70Pxxxx ordering numbers at the end of the data sheet.
NAME
PIN
TYPE DESCRIPTION
Reference Clock Input:
A required reference clock input used for clock/data recovery and frequency
synthesizer. Options include :
111
110
PI/
CI
CKREFP
CKREFN
• 139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock
input at CKREFP/N
• 17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) single-
ended CMOS clock input at CKREFP. Tie CKREFN to ground when
unused.
Receive Loss of Signal (active-high):
See Receiver Loss of Signal description for conditions.
80
19
OD/
CO
LOS1
LOS2
Receive Loss of Lock (active-high):
79
20
OD/
CO
LOL1
LOL2
This condition is met when the recovered clock frequency differs from the
reference clock frequency by more than +/- 100ppm.
Transmitter Fault Interrupt Flag (active low):
When a transmitter error event occurs (as defined in the Interrupt Control
Register Description), the INTTXxB pin will change state to indicate an
interrupt. The interrupt is cleared by a read to the STAT Register, an issue
of a FRSTx FIFO reset pulse (if the FIERRx signal caused the interrupt), or
when the TXLOL register bit transitions from high to low.
88
9
OD/
CO
INTTX1B
INTTX2B
Note: The default interrupt condition is a loss of lock in the transmitter CDR.
Receiver Fault Interrupt Flag (active low):
Reserved for future use.
70
27
OD/
CO
INTRX1B
INTRX2B
Power-On Reset (active low):
See Power-On Reset description on use of this pin.
83
A
PORB
Page: 18 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
